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5b7b41cbf2
Add the dmaengine bindings for the JZ4775 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201107122016.89859-2-zhouyanjie@wanyeetech.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
44 lines
1.3 KiB
C
44 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This header provides macros for JZ4775 DMA bindings.
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*
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* Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
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*/
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#ifndef __DT_BINDINGS_DMA_JZ4775_DMA_H__
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#define __DT_BINDINGS_DMA_JZ4775_DMA_H__
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/*
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* Request type numbers for the JZ4775 DMA controller (written to the DRTn
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* register for the channel).
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*/
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#define JZ4775_DMA_I2S0_TX 0x6
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#define JZ4775_DMA_I2S0_RX 0x7
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#define JZ4775_DMA_AUTO 0x8
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#define JZ4775_DMA_SADC_RX 0x9
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#define JZ4775_DMA_UART3_TX 0x0e
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#define JZ4775_DMA_UART3_RX 0x0f
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#define JZ4775_DMA_UART2_TX 0x10
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#define JZ4775_DMA_UART2_RX 0x11
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#define JZ4775_DMA_UART1_TX 0x12
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#define JZ4775_DMA_UART1_RX 0x13
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#define JZ4775_DMA_UART0_TX 0x14
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#define JZ4775_DMA_UART0_RX 0x15
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#define JZ4775_DMA_SSI0_TX 0x16
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#define JZ4775_DMA_SSI0_RX 0x17
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#define JZ4775_DMA_MSC0_TX 0x1a
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#define JZ4775_DMA_MSC0_RX 0x1b
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#define JZ4775_DMA_MSC1_TX 0x1c
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#define JZ4775_DMA_MSC1_RX 0x1d
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#define JZ4775_DMA_MSC2_TX 0x1e
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#define JZ4775_DMA_MSC2_RX 0x1f
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#define JZ4775_DMA_PCM0_TX 0x20
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#define JZ4775_DMA_PCM0_RX 0x21
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#define JZ4775_DMA_SMB0_TX 0x24
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#define JZ4775_DMA_SMB0_RX 0x25
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#define JZ4775_DMA_SMB1_TX 0x26
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#define JZ4775_DMA_SMB1_RX 0x27
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#define JZ4775_DMA_SMB2_TX 0x28
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#define JZ4775_DMA_SMB2_RX 0x29
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#endif /* __DT_BINDINGS_DMA_JZ4775_DMA_H__ */
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