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![AngeloGioacchino Del Regno](/assets/img/avatar_default.png)
Add a compatible string for the MT6795 Helio X10 SoC using MT8173 binding and add a header for the MT6795's GCE mailbox. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
123 lines
4.2 KiB
C
123 lines
4.2 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023 Collabora Ltd.
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* Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#ifndef _DT_BINDINGS_GCE_MT6795_H
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#define _DT_BINDINGS_GCE_MT6795_H
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/* GCE HW thread priority */
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#define CMDQ_THR_PRIO_LOWEST 0
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#define CMDQ_THR_PRIO_NORMAL 1
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#define CMDQ_THR_PRIO_NORMAL_2 2
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#define CMDQ_THR_PRIO_MEDIUM 3
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#define CMDQ_THR_PRIO_MEDIUM_2 4
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#define CMDQ_THR_PRIO_HIGH 5
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#define CMDQ_THR_PRIO_HIGHER 6
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#define CMDQ_THR_PRIO_HIGHEST 7
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/* GCE SUBSYS */
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#define SUBSYS_1300XXXX 0
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#define SUBSYS_1400XXXX 1
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#define SUBSYS_1401XXXX 2
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#define SUBSYS_1402XXXX 3
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#define SUBSYS_1500XXXX 4
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#define SUBSYS_1600XXXX 5
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#define SUBSYS_1700XXXX 6
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#define SUBSYS_1800XXXX 7
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#define SUBSYS_1000XXXX 8
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#define SUBSYS_1001XXXX 9
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#define SUBSYS_1002XXXX 10
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#define SUBSYS_1003XXXX 11
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#define SUBSYS_1004XXXX 12
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#define SUBSYS_1005XXXX 13
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#define SUBSYS_1020XXXX 14
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#define SUBSYS_1021XXXX 15
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#define SUBSYS_1120XXXX 16
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#define SUBSYS_1121XXXX 17
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#define SUBSYS_1122XXXX 18
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#define SUBSYS_1123XXXX 19
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#define SUBSYS_1124XXXX 20
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#define SUBSYS_1125XXXX 21
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#define SUBSYS_1126XXXX 22
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/* GCE HW EVENT */
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#define CMDQ_EVENT_MDP_RDMA0_SOF 0
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#define CMDQ_EVENT_MDP_RDMA1_SOF 1
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#define CMDQ_EVENT_MDP_DSI0_TE_SOF 2
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#define CMDQ_EVENT_MDP_DSI1_TE_SOF 3
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#define CMDQ_EVENT_MDP_MVW_SOF 4
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#define CMDQ_EVENT_MDP_TDSHP0_SOF 5
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#define CMDQ_EVENT_MDP_TDSHP1_SOF 6
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#define CMDQ_EVENT_MDP_WDMA_SOF 7
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#define CMDQ_EVENT_MDP_WROT0_SOF 8
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#define CMDQ_EVENT_MDP_WROT1_SOF 9
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#define CMDQ_EVENT_MDP_CROP_SOF 10
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#define CMDQ_EVENT_DISP_OVL0_SOF 11
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#define CMDQ_EVENT_DISP_OVL1_SOF 12
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#define CMDQ_EVENT_DISP_RDMA0_SOF 13
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#define CMDQ_EVENT_DISP_RDMA1_SOF 14
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#define CMDQ_EVENT_DISP_RDMA2_SOF 15
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#define CMDQ_EVENT_DISP_WDMA0_SOF 16
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#define CMDQ_EVENT_DISP_WDMA1_SOF 17
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#define CMDQ_EVENT_DISP_COLOR0_SOF 18
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#define CMDQ_EVENT_DISP_COLOR1_SOF 19
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#define CMDQ_EVENT_DISP_AAL_SOF 20
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#define CMDQ_EVENT_DISP_GAMMA_SOF 21
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#define CMDQ_EVENT_DISP_UFOE_SOF 22
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#define CMDQ_EVENT_DISP_PWM0_SOF 23
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#define CMDQ_EVENT_DISP_PWM1_SOF 24
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#define CMDQ_EVENT_DISP_OD_SOF 25
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#define CMDQ_EVENT_MDP_RDMA0_EOF 26
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#define CMDQ_EVENT_MDP_RDMA1_EOF 27
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#define CMDQ_EVENT_MDP_RSZ0_EOF 28
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#define CMDQ_EVENT_MDP_RSZ1_EOF 29
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#define CMDQ_EVENT_MDP_RSZ2_EOF 30
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#define CMDQ_EVENT_MDP_TDSHP0_EOF 31
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#define CMDQ_EVENT_MDP_TDSHP1_EOF 32
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#define CMDQ_EVENT_MDP_WDMA_EOF 33
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#define CMDQ_EVENT_MDP_WROT0_WRITE_EOF 34
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#define CMDQ_EVENT_MDP_WROT0_READ_EOF 35
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#define CMDQ_EVENT_MDP_WROT1_WRITE_EOF 36
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#define CMDQ_EVENT_MDP_WROT1_READ_EOF 37
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#define CMDQ_EVENT_MDP_CROP_EOF 38
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#define CMDQ_EVENT_DISP_OVL0_EOF 39
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#define CMDQ_EVENT_DISP_OVL1_EOF 40
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#define CMDQ_EVENT_DISP_RDMA0_EOF 41
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#define CMDQ_EVENT_DISP_RDMA1_EOF 42
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#define CMDQ_EVENT_DISP_RDMA2_EOF 43
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#define CMDQ_EVENT_DISP_WDMA0_EOF 44
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#define CMDQ_EVENT_DISP_WDMA1_EOF 45
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#define CMDQ_EVENT_DISP_COLOR0_EOF 46
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#define CMDQ_EVENT_DISP_COLOR1_EOF 47
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#define CMDQ_EVENT_DISP_AAL_EOF 48
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#define CMDQ_EVENT_DISP_GAMMA_EOF 49
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#define CMDQ_EVENT_DISP_UFOE_EOF 50
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#define CMDQ_EVENT_DISP_DPI0_EOF 51
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#define CMDQ_EVENT_MUTEX0_STREAM_EOF 52
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#define CMDQ_EVENT_MUTEX1_STREAM_EOF 53
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#define CMDQ_EVENT_MUTEX2_STREAM_EOF 54
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#define CMDQ_EVENT_MUTEX3_STREAM_EOF 55
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#define CMDQ_EVENT_MUTEX4_STREAM_EOF 56
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#define CMDQ_EVENT_MUTEX5_STREAM_EOF 57
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#define CMDQ_EVENT_MUTEX6_STREAM_EOF 58
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#define CMDQ_EVENT_MUTEX7_STREAM_EOF 59
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#define CMDQ_EVENT_MUTEX8_STREAM_EOF 60
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#define CMDQ_EVENT_MUTEX9_STREAM_EOF 61
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#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 62
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#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 63
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#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 64
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#define CMDQ_EVENT_ISP_PASS2_2_EOF 129
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#define CMDQ_EVENT_ISP_PASS2_1_EOF 130
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#define CMDQ_EVENT_ISP_PASS2_0_EOF 131
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#define CMDQ_EVENT_ISP_PASS1_1_EOF 132
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#define CMDQ_EVENT_ISP_PASS1_0_EOF 133
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#define CMDQ_EVENT_CAMSV_2_PASS1_EOF 134
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#define CMDQ_EVENT_CAMSV_1_PASS1_EOF 135
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#define CMDQ_EVENT_SENINF_CAM1_2_3_FIFO_FULL 136
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#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 137
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#define CMDQ_EVENT_JPGENC_PASS2_EOF 257
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#define CMDQ_EVENT_JPGENC_PASS1_EOF 258
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#define CMDQ_EVENT_JPGDEC_EOF 259
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#endif
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