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2c1966af07
Add a platform driver for the i.MX8MM SoC describing bus topology. Bandwidth adjustments is currently only supported on the DDRC and main NOC. Scaling for the vpu/gpu/display NICs could be added in the future. Signed-off-by: Alexandre Bailon <abailon@baylibre.com> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Link: https://lore.kernel.org/r/b14eef179dbd837a486619724b8033490f49db72.1586174566.git.leonard.crestez@nxp.com Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
50 lines
1.1 KiB
C
50 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Interconnect framework driver for i.MX SoC
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*
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* Copyright (c) 2019, BayLibre
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* Copyright (c) 2019-2020, NXP
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* Author: Alexandre Bailon <abailon@baylibre.com>
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*/
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#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MM_H
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#define __DT_BINDINGS_INTERCONNECT_IMX8MM_H
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#define IMX8MM_ICN_NOC 1
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#define IMX8MM_ICS_DRAM 2
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#define IMX8MM_ICS_OCRAM 3
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#define IMX8MM_ICM_A53 4
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#define IMX8MM_ICM_VPU_H1 5
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#define IMX8MM_ICM_VPU_G1 6
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#define IMX8MM_ICM_VPU_G2 7
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#define IMX8MM_ICN_VIDEO 8
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#define IMX8MM_ICM_GPU2D 9
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#define IMX8MM_ICM_GPU3D 10
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#define IMX8MM_ICN_GPU 11
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#define IMX8MM_ICM_CSI 12
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#define IMX8MM_ICM_LCDIF 13
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#define IMX8MM_ICN_MIPI 14
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#define IMX8MM_ICM_USB1 15
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#define IMX8MM_ICM_USB2 16
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#define IMX8MM_ICM_PCIE 17
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#define IMX8MM_ICN_HSIO 18
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#define IMX8MM_ICM_SDMA2 19
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#define IMX8MM_ICM_SDMA3 20
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#define IMX8MM_ICN_AUDIO 21
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#define IMX8MM_ICN_ENET 22
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#define IMX8MM_ICM_ENET 23
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#define IMX8MM_ICN_MAIN 24
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#define IMX8MM_ICM_NAND 25
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#define IMX8MM_ICM_SDMA1 26
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#define IMX8MM_ICM_USDHC1 27
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#define IMX8MM_ICM_USDHC2 28
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#define IMX8MM_ICM_USDHC3 29
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#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MM_H */
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