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8742bb4bf2
The QUP ports exist in the topology, but are not exposed as an endpoints in DT. Fix this by creating IDs and attach them to their NoCs, so that the various QUP drivers (i2c/spi/uart etc.) are able to request their interconnect paths and scale their bandwidth. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Link: https://lore.kernel.org/r/20201105135211.7160-1-georgi.djakov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
150 lines
3.9 KiB
C
150 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Qualcomm SDM845 interconnect IDs
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*
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* Copyright (c) 2018, Linaro Ltd.
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* Author: Georgi Djakov <georgi.djakov@linaro.org>
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*/
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#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H
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#define __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H
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#define MASTER_A1NOC_CFG 0
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#define MASTER_TSIF 1
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#define MASTER_SDCC_2 2
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#define MASTER_SDCC_4 3
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#define MASTER_UFS_CARD 4
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#define MASTER_UFS_MEM 5
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#define MASTER_PCIE_0 6
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#define SLAVE_A1NOC_SNOC 7
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#define SLAVE_SERVICE_A1NOC 8
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#define SLAVE_ANOC_PCIE_A1NOC_SNOC 9
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#define MASTER_QUP_1 10
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#define MASTER_A2NOC_CFG 0
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#define MASTER_QDSS_BAM 1
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#define MASTER_CNOC_A2NOC 2
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#define MASTER_CRYPTO 3
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#define MASTER_IPA 4
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#define MASTER_PCIE_1 5
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#define MASTER_QDSS_ETR 6
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#define MASTER_USB3_0 7
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#define MASTER_USB3_1 8
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#define SLAVE_A2NOC_SNOC 9
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#define SLAVE_ANOC_PCIE_SNOC 10
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#define SLAVE_SERVICE_A2NOC 11
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#define MASTER_QUP_2 12
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#define MASTER_SPDM 0
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#define MASTER_TIC 1
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#define MASTER_SNOC_CNOC 2
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#define MASTER_QDSS_DAP 3
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#define SLAVE_A1NOC_CFG 4
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#define SLAVE_A2NOC_CFG 5
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#define SLAVE_AOP 6
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#define SLAVE_AOSS 7
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#define SLAVE_CAMERA_CFG 8
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#define SLAVE_CLK_CTL 9
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#define SLAVE_CDSP_CFG 10
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#define SLAVE_RBCPR_CX_CFG 11
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#define SLAVE_CRYPTO_0_CFG 12
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#define SLAVE_DCC_CFG 13
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#define SLAVE_CNOC_DDRSS 14
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#define SLAVE_DISPLAY_CFG 15
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#define SLAVE_GLM 16
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#define SLAVE_GFX3D_CFG 17
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#define SLAVE_IMEM_CFG 18
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#define SLAVE_IPA_CFG 19
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#define SLAVE_CNOC_MNOC_CFG 20
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#define SLAVE_PCIE_0_CFG 21
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#define SLAVE_PCIE_1_CFG 22
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#define SLAVE_PDM 23
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#define SLAVE_SOUTH_PHY_CFG 24
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#define SLAVE_PIMEM_CFG 25
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#define SLAVE_PRNG 26
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#define SLAVE_QDSS_CFG 27
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#define SLAVE_BLSP_2 28
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#define SLAVE_BLSP_1 29
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#define SLAVE_SDCC_2 30
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#define SLAVE_SDCC_4 31
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#define SLAVE_SNOC_CFG 32
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#define SLAVE_SPDM_WRAPPER 33
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#define SLAVE_SPSS_CFG 34
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#define SLAVE_TCSR 35
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#define SLAVE_TLMM_NORTH 36
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#define SLAVE_TLMM_SOUTH 37
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#define SLAVE_TSIF 38
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#define SLAVE_UFS_CARD_CFG 39
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#define SLAVE_UFS_MEM_CFG 40
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#define SLAVE_USB3_0 41
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#define SLAVE_USB3_1 42
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#define SLAVE_VENUS_CFG 43
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#define SLAVE_VSENSE_CTRL_CFG 44
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#define SLAVE_CNOC_A2NOC 45
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#define SLAVE_SERVICE_CNOC 46
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#define MASTER_CNOC_DC_NOC 0
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#define SLAVE_LLCC_CFG 1
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#define SLAVE_MEM_NOC_CFG 2
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#define MASTER_APPSS_PROC 0
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#define MASTER_GNOC_CFG 1
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#define SLAVE_GNOC_SNOC 2
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#define SLAVE_GNOC_MEM_NOC 3
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#define SLAVE_SERVICE_GNOC 4
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#define MASTER_TCU_0 0
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#define MASTER_MEM_NOC_CFG 1
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#define MASTER_GNOC_MEM_NOC 2
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#define MASTER_MNOC_HF_MEM_NOC 3
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#define MASTER_MNOC_SF_MEM_NOC 4
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#define MASTER_SNOC_GC_MEM_NOC 5
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#define MASTER_SNOC_SF_MEM_NOC 6
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#define MASTER_GFX3D 7
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#define SLAVE_MSS_PROC_MS_MPU_CFG 8
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#define SLAVE_MEM_NOC_GNOC 9
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#define SLAVE_LLCC 10
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#define SLAVE_MEM_NOC_SNOC 11
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#define SLAVE_SERVICE_MEM_NOC 12
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#define MASTER_LLCC 13
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#define SLAVE_EBI1 14
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#define MASTER_CNOC_MNOC_CFG 0
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#define MASTER_CAMNOC_HF0 1
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#define MASTER_CAMNOC_HF1 2
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#define MASTER_CAMNOC_SF 3
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#define MASTER_MDP0 4
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#define MASTER_MDP1 5
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#define MASTER_ROTATOR 6
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#define MASTER_VIDEO_P0 7
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#define MASTER_VIDEO_P1 8
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#define MASTER_VIDEO_PROC 9
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#define SLAVE_MNOC_SF_MEM_NOC 10
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#define SLAVE_MNOC_HF_MEM_NOC 11
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#define SLAVE_SERVICE_MNOC 12
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#define MASTER_CAMNOC_HF0_UNCOMP 13
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#define MASTER_CAMNOC_HF1_UNCOMP 14
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#define MASTER_CAMNOC_SF_UNCOMP 15
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#define SLAVE_CAMNOC_UNCOMP 16
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#define MASTER_SNOC_CFG 0
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#define MASTER_A1NOC_SNOC 1
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#define MASTER_A2NOC_SNOC 2
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#define MASTER_GNOC_SNOC 3
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#define MASTER_MEM_NOC_SNOC 4
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#define MASTER_ANOC_PCIE_SNOC 5
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#define MASTER_PIMEM 6
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#define MASTER_GIC 7
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#define SLAVE_APPSS 8
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#define SLAVE_SNOC_CNOC 9
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#define SLAVE_SNOC_MEM_NOC_GC 10
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#define SLAVE_SNOC_MEM_NOC_SF 11
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#define SLAVE_IMEM 12
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#define SLAVE_PCIE_0 13
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#define SLAVE_PCIE_1 14
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#define SLAVE_PIMEM 15
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#define SLAVE_SERVICE_SNOC 16
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#define SLAVE_QDSS_STM 17
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#define SLAVE_TCU 18
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#endif
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