mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
162 lines
4.4 KiB
ArmAsm
162 lines
4.4 KiB
ArmAsm
@ Read/Write DMA code for the ST506/MFM hard drive controllers on the A400 Acorn Archimedes
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@ motherboard and on ST506 expansion podules.
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@ (c) David Alan Gilbert (linux@treblig.org) 1996-1999
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#include <asm/assembler.h>
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hdc63463_irqdata:
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@ Controller base address
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.global hdc63463_baseaddress
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hdc63463_baseaddress:
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.word 0
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.global hdc63463_irqpolladdress
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hdc63463_irqpolladdress:
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.word 0
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.global hdc63463_irqpollmask
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hdc63463_irqpollmask:
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.word 0
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@ where to read/write data from the kernel data space
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.global hdc63463_dataptr
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hdc63463_dataptr:
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.word 0
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@ Number of bytes left to transfer
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.global hdc63463_dataleft
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hdc63463_dataleft:
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.word 0
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@ -------------------------------------------------------------------------
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@ hdc63463_writedma: DMA from host to controller
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@ internal reg usage: r0=hdc base address, r1=irq poll address, r2=poll mask
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@ r3=data ptr, r4=data left, r5,r6=temporary
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.global hdc63463_writedma
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hdc63463_writedma:
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stmfd sp!,{r4-r7}
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adr r5,hdc63463_irqdata
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ldmia r5,{r0,r1,r2,r3,r4}
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writedma_again:
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@ test number of remaining bytes to transfer
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cmp r4,#0
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beq writedma_end
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bmi writedma_end
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@ Check the hdc is interrupting
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ldrb r5,[r1,#0]
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tst r5,r2
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beq writedma_end
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@ Transfer a block of upto 256 bytes
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cmp r4,#256
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movlt r7,r4
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movge r7,#256
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@ Check the hdc is still busy and command has not ended and no errors
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ldr r5,[r0,#32] @ Status reg - 16 bit - its the top few bits which are status
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@ think we should continue DMA until it drops busy - perhaps this was
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@ the main problem with corrected errors causing a hang
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@tst r5,#0x3c00 @ Test for things which should be off
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@bne writedma_end
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and r5,r5,#0x8000 @ This is test for things which should be on: Busy
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cmp r5,#0x8000
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bne writedma_end
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@ Bytes remaining at end
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sub r4,r4,r7
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@ HDC Write register location
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add r0,r0,#32+8
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writedma_loop:
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@ OK - pretty sure we should be doing this
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ldr r5,[r3],#4 @ Get a word to be written
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@ get bottom half to be sent first
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mov r6,r5,lsl#16 @ Separate the first 2 bytes
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orr r2,r6,r6,lsr #16 @ Duplicate them in the bottom half of the word
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@ now the top half
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mov r6,r5,lsr#16 @ Get 2nd 2 bytes
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orr r6,r6,r6,lsl#16 @ Duplicate
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@str r6,[r0] @ to hdc
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stmia r0,{r2,r6}
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subs r7,r7,#4 @ Dec. number of bytes left
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bne writedma_loop
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@ If we were too slow we had better go through again - DAG - took out with new interrupt routine
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@ sub r0,r0,#32+8
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@ adr r2,hdc63463_irqdata
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@ ldr r2,[r2,#8]
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@ b writedma_again
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writedma_end:
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adr r5,hdc63463_irqdata+12
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stmia r5,{r3,r4}
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ldmfd sp!,{r4-r7}
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RETINSTR(mov,pc,lr)
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@ -------------------------------------------------------------------------
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@ hdc63463_readdma: DMA from controller to host
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@ internal reg usage: r0=hdc base address, r1=irq poll address, r2=poll mask
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@ r3=data ptr, r4=data left, r5,r6=temporary
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.global hdc63463_readdma
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hdc63463_readdma:
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stmfd sp!,{r4-r7}
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adr r5,hdc63463_irqdata
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ldmia r5,{r0,r1,r2,r3,r4}
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readdma_again:
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@ test number of remaining bytes to transfer
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cmp r4,#0
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beq readdma_end
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bmi readdma_end
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@ Check the hdc is interrupting
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ldrb r5,[r1,#0]
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tst r5,r2
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beq readdma_end
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@ Check the hdc is still busy and command has not ended and no errors
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ldr r5,[r0,#32] @ Status reg - 16 bit - its the top few bits which are status
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@ think we should continue DMA until it drops busy - perhaps this was
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@ the main problem with corrected errors causing a hang
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@tst r5,#0x3c00 @ Test for things which should be off
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@bne readdma_end
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and r5,r5,#0x8000 @ This is test for things which should be on: Busy
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cmp r5,#0x8000
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bne readdma_end
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@ Transfer a block of upto 256 bytes
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cmp r4,#256
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movlt r7,r4
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movge r7,#256
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@ Bytes remaining at end
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sub r4,r4,r7
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@ Set a pointer to the data register in the HDC
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add r0,r0,#8
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readdma_loop:
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@ OK - pretty sure we should be doing this
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ldmia r0,{r5,r6}
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mov r5,r5,lsl#16
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mov r6,r6,lsl#16
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orr r6,r6,r5,lsr #16
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str r6,[r3],#4
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subs r7,r7,#4 @ Decrement bytes to go
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bne readdma_loop
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@ Try reading multiple blocks - if this was fast enough then I do not think
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@ this should help - NO taken out DAG - new interrupt handler has
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@ non-consecutive memory blocks
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@ sub r0,r0,#8
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@ b readdma_again
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readdma_end:
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adr r5,hdc63463_irqdata+12
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stmia r5,{r3,r4}
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ldmfd sp!,{r4-r7}
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RETINSTR(mov,pc,lr)
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