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1109 lines
29 KiB
C
1109 lines
29 KiB
C
/*
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* libata-bmdma.c - helper library for PCI IDE BMDMA
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*
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* Maintained by: Jeff Garzik <jgarzik@pobox.com>
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* Please ALWAYS copy linux-ide@vger.kernel.org
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* on emails.
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*
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* Copyright 2003-2006 Red Hat, Inc. All rights reserved.
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* Copyright 2003-2006 Jeff Garzik
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* libata documentation is available via 'make {ps|pdf}docs',
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* as Documentation/DocBook/libata.*
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*
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* Hardware documentation available from http://www.t13.org/ and
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* http://www.sata-io.org/
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*
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/libata.h>
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#include "libata.h"
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/**
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* ata_tf_load_pio - send taskfile registers to host controller
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* @ap: Port to which output is sent
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* @tf: ATA taskfile register set
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*
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* Outputs ATA taskfile to standard ATA host controller.
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*
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* LOCKING:
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* Inherited from caller.
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*/
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static void ata_tf_load_pio(struct ata_port *ap, const struct ata_taskfile *tf)
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{
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struct ata_ioports *ioaddr = &ap->ioaddr;
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unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
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if (tf->ctl != ap->last_ctl) {
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outb(tf->ctl, ioaddr->ctl_addr);
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ap->last_ctl = tf->ctl;
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ata_wait_idle(ap);
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}
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if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
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outb(tf->hob_feature, ioaddr->feature_addr);
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outb(tf->hob_nsect, ioaddr->nsect_addr);
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outb(tf->hob_lbal, ioaddr->lbal_addr);
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outb(tf->hob_lbam, ioaddr->lbam_addr);
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outb(tf->hob_lbah, ioaddr->lbah_addr);
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VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
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tf->hob_feature,
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tf->hob_nsect,
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tf->hob_lbal,
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tf->hob_lbam,
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tf->hob_lbah);
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}
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if (is_addr) {
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outb(tf->feature, ioaddr->feature_addr);
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outb(tf->nsect, ioaddr->nsect_addr);
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outb(tf->lbal, ioaddr->lbal_addr);
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outb(tf->lbam, ioaddr->lbam_addr);
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outb(tf->lbah, ioaddr->lbah_addr);
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VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
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tf->feature,
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tf->nsect,
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tf->lbal,
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tf->lbam,
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tf->lbah);
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}
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if (tf->flags & ATA_TFLAG_DEVICE) {
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outb(tf->device, ioaddr->device_addr);
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VPRINTK("device 0x%X\n", tf->device);
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}
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ata_wait_idle(ap);
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}
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/**
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* ata_tf_load_mmio - send taskfile registers to host controller
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* @ap: Port to which output is sent
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* @tf: ATA taskfile register set
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*
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* Outputs ATA taskfile to standard ATA host controller using MMIO.
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*
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* LOCKING:
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* Inherited from caller.
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*/
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static void ata_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
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{
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struct ata_ioports *ioaddr = &ap->ioaddr;
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unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
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if (tf->ctl != ap->last_ctl) {
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writeb(tf->ctl, (void __iomem *) ap->ioaddr.ctl_addr);
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ap->last_ctl = tf->ctl;
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ata_wait_idle(ap);
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}
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if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
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writeb(tf->hob_feature, (void __iomem *) ioaddr->feature_addr);
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writeb(tf->hob_nsect, (void __iomem *) ioaddr->nsect_addr);
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writeb(tf->hob_lbal, (void __iomem *) ioaddr->lbal_addr);
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writeb(tf->hob_lbam, (void __iomem *) ioaddr->lbam_addr);
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writeb(tf->hob_lbah, (void __iomem *) ioaddr->lbah_addr);
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VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
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tf->hob_feature,
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tf->hob_nsect,
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tf->hob_lbal,
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tf->hob_lbam,
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tf->hob_lbah);
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}
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if (is_addr) {
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writeb(tf->feature, (void __iomem *) ioaddr->feature_addr);
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writeb(tf->nsect, (void __iomem *) ioaddr->nsect_addr);
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writeb(tf->lbal, (void __iomem *) ioaddr->lbal_addr);
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writeb(tf->lbam, (void __iomem *) ioaddr->lbam_addr);
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writeb(tf->lbah, (void __iomem *) ioaddr->lbah_addr);
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VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
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tf->feature,
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tf->nsect,
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tf->lbal,
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tf->lbam,
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tf->lbah);
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}
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if (tf->flags & ATA_TFLAG_DEVICE) {
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writeb(tf->device, (void __iomem *) ioaddr->device_addr);
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VPRINTK("device 0x%X\n", tf->device);
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}
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ata_wait_idle(ap);
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}
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/**
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* ata_tf_load - send taskfile registers to host controller
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* @ap: Port to which output is sent
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* @tf: ATA taskfile register set
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*
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* Outputs ATA taskfile to standard ATA host controller using MMIO
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* or PIO as indicated by the ATA_FLAG_MMIO flag.
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* Writes the control, feature, nsect, lbal, lbam, and lbah registers.
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* Optionally (ATA_TFLAG_LBA48) writes hob_feature, hob_nsect,
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* hob_lbal, hob_lbam, and hob_lbah.
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*
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* This function waits for idle (!BUSY and !DRQ) after writing
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* registers. If the control register has a new value, this
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* function also waits for idle after writing control and before
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* writing the remaining registers.
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*
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* May be used as the tf_load() entry in ata_port_operations.
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*
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* LOCKING:
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* Inherited from caller.
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*/
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void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
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{
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if (ap->flags & ATA_FLAG_MMIO)
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ata_tf_load_mmio(ap, tf);
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else
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ata_tf_load_pio(ap, tf);
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}
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/**
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* ata_exec_command_pio - issue ATA command to host controller
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* @ap: port to which command is being issued
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* @tf: ATA taskfile register set
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*
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* Issues PIO write to ATA command register, with proper
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* synchronization with interrupt handler / other threads.
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*
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* LOCKING:
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* spin_lock_irqsave(host_set lock)
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*/
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static void ata_exec_command_pio(struct ata_port *ap, const struct ata_taskfile *tf)
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{
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DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command);
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outb(tf->command, ap->ioaddr.command_addr);
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ata_pause(ap);
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}
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/**
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* ata_exec_command_mmio - issue ATA command to host controller
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* @ap: port to which command is being issued
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* @tf: ATA taskfile register set
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*
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* Issues MMIO write to ATA command register, with proper
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* synchronization with interrupt handler / other threads.
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*
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* FIXME: missing write posting for 400nS delay enforcement
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*
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* LOCKING:
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* spin_lock_irqsave(host_set lock)
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*/
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static void ata_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
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{
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DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command);
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writeb(tf->command, (void __iomem *) ap->ioaddr.command_addr);
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ata_pause(ap);
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}
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/**
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* ata_exec_command - issue ATA command to host controller
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* @ap: port to which command is being issued
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* @tf: ATA taskfile register set
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*
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* Issues PIO/MMIO write to ATA command register, with proper
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* synchronization with interrupt handler / other threads.
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*
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* LOCKING:
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* spin_lock_irqsave(host_set lock)
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*/
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void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
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{
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if (ap->flags & ATA_FLAG_MMIO)
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ata_exec_command_mmio(ap, tf);
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else
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ata_exec_command_pio(ap, tf);
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}
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/**
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* ata_tf_read_pio - input device's ATA taskfile shadow registers
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* @ap: Port from which input is read
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* @tf: ATA taskfile register set for storing input
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*
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* Reads ATA taskfile registers for currently-selected device
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* into @tf.
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*
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* LOCKING:
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* Inherited from caller.
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*/
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static void ata_tf_read_pio(struct ata_port *ap, struct ata_taskfile *tf)
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{
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struct ata_ioports *ioaddr = &ap->ioaddr;
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tf->command = ata_check_status(ap);
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tf->feature = inb(ioaddr->error_addr);
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tf->nsect = inb(ioaddr->nsect_addr);
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tf->lbal = inb(ioaddr->lbal_addr);
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tf->lbam = inb(ioaddr->lbam_addr);
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tf->lbah = inb(ioaddr->lbah_addr);
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tf->device = inb(ioaddr->device_addr);
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if (tf->flags & ATA_TFLAG_LBA48) {
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outb(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
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tf->hob_feature = inb(ioaddr->error_addr);
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tf->hob_nsect = inb(ioaddr->nsect_addr);
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tf->hob_lbal = inb(ioaddr->lbal_addr);
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tf->hob_lbam = inb(ioaddr->lbam_addr);
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tf->hob_lbah = inb(ioaddr->lbah_addr);
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}
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}
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/**
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* ata_tf_read_mmio - input device's ATA taskfile shadow registers
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* @ap: Port from which input is read
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* @tf: ATA taskfile register set for storing input
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*
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* Reads ATA taskfile registers for currently-selected device
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* into @tf via MMIO.
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*
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* LOCKING:
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* Inherited from caller.
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*/
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static void ata_tf_read_mmio(struct ata_port *ap, struct ata_taskfile *tf)
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{
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struct ata_ioports *ioaddr = &ap->ioaddr;
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tf->command = ata_check_status(ap);
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tf->feature = readb((void __iomem *)ioaddr->error_addr);
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tf->nsect = readb((void __iomem *)ioaddr->nsect_addr);
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tf->lbal = readb((void __iomem *)ioaddr->lbal_addr);
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tf->lbam = readb((void __iomem *)ioaddr->lbam_addr);
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tf->lbah = readb((void __iomem *)ioaddr->lbah_addr);
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tf->device = readb((void __iomem *)ioaddr->device_addr);
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if (tf->flags & ATA_TFLAG_LBA48) {
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writeb(tf->ctl | ATA_HOB, (void __iomem *) ap->ioaddr.ctl_addr);
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tf->hob_feature = readb((void __iomem *)ioaddr->error_addr);
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tf->hob_nsect = readb((void __iomem *)ioaddr->nsect_addr);
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tf->hob_lbal = readb((void __iomem *)ioaddr->lbal_addr);
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tf->hob_lbam = readb((void __iomem *)ioaddr->lbam_addr);
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tf->hob_lbah = readb((void __iomem *)ioaddr->lbah_addr);
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}
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}
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/**
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* ata_tf_read - input device's ATA taskfile shadow registers
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* @ap: Port from which input is read
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* @tf: ATA taskfile register set for storing input
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*
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* Reads ATA taskfile registers for currently-selected device
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* into @tf.
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*
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* Reads nsect, lbal, lbam, lbah, and device. If ATA_TFLAG_LBA48
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* is set, also reads the hob registers.
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*
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* May be used as the tf_read() entry in ata_port_operations.
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*
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* LOCKING:
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* Inherited from caller.
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*/
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void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
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{
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if (ap->flags & ATA_FLAG_MMIO)
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ata_tf_read_mmio(ap, tf);
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else
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ata_tf_read_pio(ap, tf);
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}
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/**
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* ata_check_status_pio - Read device status reg & clear interrupt
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* @ap: port where the device is
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*
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* Reads ATA taskfile status register for currently-selected device
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* and return its value. This also clears pending interrupts
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* from this device
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*
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* LOCKING:
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* Inherited from caller.
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*/
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static u8 ata_check_status_pio(struct ata_port *ap)
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{
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return inb(ap->ioaddr.status_addr);
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}
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/**
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* ata_check_status_mmio - Read device status reg & clear interrupt
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* @ap: port where the device is
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*
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* Reads ATA taskfile status register for currently-selected device
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* via MMIO and return its value. This also clears pending interrupts
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* from this device
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*
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* LOCKING:
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* Inherited from caller.
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*/
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static u8 ata_check_status_mmio(struct ata_port *ap)
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{
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return readb((void __iomem *) ap->ioaddr.status_addr);
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}
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/**
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* ata_check_status - Read device status reg & clear interrupt
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* @ap: port where the device is
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*
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* Reads ATA taskfile status register for currently-selected device
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* and return its value. This also clears pending interrupts
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* from this device
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*
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* May be used as the check_status() entry in ata_port_operations.
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*
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* LOCKING:
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* Inherited from caller.
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*/
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u8 ata_check_status(struct ata_port *ap)
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{
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if (ap->flags & ATA_FLAG_MMIO)
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return ata_check_status_mmio(ap);
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return ata_check_status_pio(ap);
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}
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/**
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* ata_altstatus - Read device alternate status reg
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* @ap: port where the device is
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*
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* Reads ATA taskfile alternate status register for
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* currently-selected device and return its value.
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*
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* Note: may NOT be used as the check_altstatus() entry in
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* ata_port_operations.
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*
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* LOCKING:
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* Inherited from caller.
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*/
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u8 ata_altstatus(struct ata_port *ap)
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{
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if (ap->ops->check_altstatus)
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return ap->ops->check_altstatus(ap);
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if (ap->flags & ATA_FLAG_MMIO)
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return readb((void __iomem *)ap->ioaddr.altstatus_addr);
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return inb(ap->ioaddr.altstatus_addr);
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}
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/**
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* ata_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction
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* @qc: Info associated with this ATA transaction.
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*
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* LOCKING:
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* spin_lock_irqsave(host_set lock)
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*/
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static void ata_bmdma_setup_mmio (struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
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u8 dmactl;
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void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
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/* load PRD table addr. */
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mb(); /* make sure PRD table writes are visible to controller */
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writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
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/* specify data direction, triple-check start bit is clear */
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dmactl = readb(mmio + ATA_DMA_CMD);
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dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
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if (!rw)
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dmactl |= ATA_DMA_WR;
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writeb(dmactl, mmio + ATA_DMA_CMD);
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/* issue r/w command */
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ap->ops->exec_command(ap, &qc->tf);
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}
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/**
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* ata_bmdma_start_mmio - Start a PCI IDE BMDMA transaction
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* @qc: Info associated with this ATA transaction.
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*
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* LOCKING:
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* spin_lock_irqsave(host_set lock)
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*/
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static void ata_bmdma_start_mmio (struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
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u8 dmactl;
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/* start host DMA transaction */
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dmactl = readb(mmio + ATA_DMA_CMD);
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writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
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|
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/* Strictly, one may wish to issue a readb() here, to
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* flush the mmio write. However, control also passes
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* to the hardware at this point, and it will interrupt
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* us when we are to resume control. So, in effect,
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* we don't care when the mmio write flushes.
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|
* Further, a read of the DMA status register _immediately_
|
|
* following the write may not be what certain flaky hardware
|
|
* is expected, so I think it is best to not add a readb()
|
|
* without first all the MMIO ATA cards/mobos.
|
|
* Or maybe I'm just being paranoid.
|
|
*/
|
|
}
|
|
|
|
/**
|
|
* ata_bmdma_setup_pio - Set up PCI IDE BMDMA transaction (PIO)
|
|
* @qc: Info associated with this ATA transaction.
|
|
*
|
|
* LOCKING:
|
|
* spin_lock_irqsave(host_set lock)
|
|
*/
|
|
|
|
static void ata_bmdma_setup_pio (struct ata_queued_cmd *qc)
|
|
{
|
|
struct ata_port *ap = qc->ap;
|
|
unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
|
|
u8 dmactl;
|
|
|
|
/* load PRD table addr. */
|
|
outl(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
|
|
|
|
/* specify data direction, triple-check start bit is clear */
|
|
dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
|
|
dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
|
|
if (!rw)
|
|
dmactl |= ATA_DMA_WR;
|
|
outb(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
|
|
|
|
/* issue r/w command */
|
|
ap->ops->exec_command(ap, &qc->tf);
|
|
}
|
|
|
|
/**
|
|
* ata_bmdma_start_pio - Start a PCI IDE BMDMA transaction (PIO)
|
|
* @qc: Info associated with this ATA transaction.
|
|
*
|
|
* LOCKING:
|
|
* spin_lock_irqsave(host_set lock)
|
|
*/
|
|
|
|
static void ata_bmdma_start_pio (struct ata_queued_cmd *qc)
|
|
{
|
|
struct ata_port *ap = qc->ap;
|
|
u8 dmactl;
|
|
|
|
/* start host DMA transaction */
|
|
dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
|
|
outb(dmactl | ATA_DMA_START,
|
|
ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
|
|
}
|
|
|
|
|
|
/**
|
|
* ata_bmdma_start - Start a PCI IDE BMDMA transaction
|
|
* @qc: Info associated with this ATA transaction.
|
|
*
|
|
* Writes the ATA_DMA_START flag to the DMA command register.
|
|
*
|
|
* May be used as the bmdma_start() entry in ata_port_operations.
|
|
*
|
|
* LOCKING:
|
|
* spin_lock_irqsave(host_set lock)
|
|
*/
|
|
void ata_bmdma_start(struct ata_queued_cmd *qc)
|
|
{
|
|
if (qc->ap->flags & ATA_FLAG_MMIO)
|
|
ata_bmdma_start_mmio(qc);
|
|
else
|
|
ata_bmdma_start_pio(qc);
|
|
}
|
|
|
|
|
|
/**
|
|
* ata_bmdma_setup - Set up PCI IDE BMDMA transaction
|
|
* @qc: Info associated with this ATA transaction.
|
|
*
|
|
* Writes address of PRD table to device's PRD Table Address
|
|
* register, sets the DMA control register, and calls
|
|
* ops->exec_command() to start the transfer.
|
|
*
|
|
* May be used as the bmdma_setup() entry in ata_port_operations.
|
|
*
|
|
* LOCKING:
|
|
* spin_lock_irqsave(host_set lock)
|
|
*/
|
|
void ata_bmdma_setup(struct ata_queued_cmd *qc)
|
|
{
|
|
if (qc->ap->flags & ATA_FLAG_MMIO)
|
|
ata_bmdma_setup_mmio(qc);
|
|
else
|
|
ata_bmdma_setup_pio(qc);
|
|
}
|
|
|
|
|
|
/**
|
|
* ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
|
|
* @ap: Port associated with this ATA transaction.
|
|
*
|
|
* Clear interrupt and error flags in DMA status register.
|
|
*
|
|
* May be used as the irq_clear() entry in ata_port_operations.
|
|
*
|
|
* LOCKING:
|
|
* spin_lock_irqsave(host_set lock)
|
|
*/
|
|
|
|
void ata_bmdma_irq_clear(struct ata_port *ap)
|
|
{
|
|
if (!ap->ioaddr.bmdma_addr)
|
|
return;
|
|
|
|
if (ap->flags & ATA_FLAG_MMIO) {
|
|
void __iomem *mmio =
|
|
((void __iomem *) ap->ioaddr.bmdma_addr) + ATA_DMA_STATUS;
|
|
writeb(readb(mmio), mmio);
|
|
} else {
|
|
unsigned long addr = ap->ioaddr.bmdma_addr + ATA_DMA_STATUS;
|
|
outb(inb(addr), addr);
|
|
}
|
|
}
|
|
|
|
|
|
/**
|
|
* ata_bmdma_status - Read PCI IDE BMDMA status
|
|
* @ap: Port associated with this ATA transaction.
|
|
*
|
|
* Read and return BMDMA status register.
|
|
*
|
|
* May be used as the bmdma_status() entry in ata_port_operations.
|
|
*
|
|
* LOCKING:
|
|
* spin_lock_irqsave(host_set lock)
|
|
*/
|
|
|
|
u8 ata_bmdma_status(struct ata_port *ap)
|
|
{
|
|
u8 host_stat;
|
|
if (ap->flags & ATA_FLAG_MMIO) {
|
|
void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
|
|
host_stat = readb(mmio + ATA_DMA_STATUS);
|
|
} else
|
|
host_stat = inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
|
|
return host_stat;
|
|
}
|
|
|
|
|
|
/**
|
|
* ata_bmdma_stop - Stop PCI IDE BMDMA transfer
|
|
* @qc: Command we are ending DMA for
|
|
*
|
|
* Clears the ATA_DMA_START flag in the dma control register
|
|
*
|
|
* May be used as the bmdma_stop() entry in ata_port_operations.
|
|
*
|
|
* LOCKING:
|
|
* spin_lock_irqsave(host_set lock)
|
|
*/
|
|
|
|
void ata_bmdma_stop(struct ata_queued_cmd *qc)
|
|
{
|
|
struct ata_port *ap = qc->ap;
|
|
if (ap->flags & ATA_FLAG_MMIO) {
|
|
void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
|
|
|
|
/* clear start/stop bit */
|
|
writeb(readb(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
|
|
mmio + ATA_DMA_CMD);
|
|
} else {
|
|
/* clear start/stop bit */
|
|
outb(inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD) & ~ATA_DMA_START,
|
|
ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
|
|
}
|
|
|
|
/* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
|
|
ata_altstatus(ap); /* dummy read */
|
|
}
|
|
|
|
/**
|
|
* ata_bmdma_freeze - Freeze BMDMA controller port
|
|
* @ap: port to freeze
|
|
*
|
|
* Freeze BMDMA controller port.
|
|
*
|
|
* LOCKING:
|
|
* Inherited from caller.
|
|
*/
|
|
void ata_bmdma_freeze(struct ata_port *ap)
|
|
{
|
|
struct ata_ioports *ioaddr = &ap->ioaddr;
|
|
|
|
ap->ctl |= ATA_NIEN;
|
|
ap->last_ctl = ap->ctl;
|
|
|
|
if (ap->flags & ATA_FLAG_MMIO)
|
|
writeb(ap->ctl, (void __iomem *)ioaddr->ctl_addr);
|
|
else
|
|
outb(ap->ctl, ioaddr->ctl_addr);
|
|
}
|
|
|
|
/**
|
|
* ata_bmdma_thaw - Thaw BMDMA controller port
|
|
* @ap: port to thaw
|
|
*
|
|
* Thaw BMDMA controller port.
|
|
*
|
|
* LOCKING:
|
|
* Inherited from caller.
|
|
*/
|
|
void ata_bmdma_thaw(struct ata_port *ap)
|
|
{
|
|
/* clear & re-enable interrupts */
|
|
ata_chk_status(ap);
|
|
ap->ops->irq_clear(ap);
|
|
if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
|
|
ata_irq_on(ap);
|
|
}
|
|
|
|
/**
|
|
* ata_bmdma_drive_eh - Perform EH with given methods for BMDMA controller
|
|
* @ap: port to handle error for
|
|
* @prereset: prereset method (can be NULL)
|
|
* @softreset: softreset method (can be NULL)
|
|
* @hardreset: hardreset method (can be NULL)
|
|
* @postreset: postreset method (can be NULL)
|
|
*
|
|
* Handle error for ATA BMDMA controller. It can handle both
|
|
* PATA and SATA controllers. Many controllers should be able to
|
|
* use this EH as-is or with some added handling before and
|
|
* after.
|
|
*
|
|
* This function is intended to be used for constructing
|
|
* ->error_handler callback by low level drivers.
|
|
*
|
|
* LOCKING:
|
|
* Kernel thread context (may sleep)
|
|
*/
|
|
void ata_bmdma_drive_eh(struct ata_port *ap, ata_prereset_fn_t prereset,
|
|
ata_reset_fn_t softreset, ata_reset_fn_t hardreset,
|
|
ata_postreset_fn_t postreset)
|
|
{
|
|
struct ata_eh_context *ehc = &ap->eh_context;
|
|
struct ata_queued_cmd *qc;
|
|
unsigned long flags;
|
|
int thaw = 0;
|
|
|
|
qc = __ata_qc_from_tag(ap, ap->active_tag);
|
|
if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
|
|
qc = NULL;
|
|
|
|
/* reset PIO HSM and stop DMA engine */
|
|
spin_lock_irqsave(ap->lock, flags);
|
|
|
|
ap->hsm_task_state = HSM_ST_IDLE;
|
|
|
|
if (qc && (qc->tf.protocol == ATA_PROT_DMA ||
|
|
qc->tf.protocol == ATA_PROT_ATAPI_DMA)) {
|
|
u8 host_stat;
|
|
|
|
host_stat = ata_bmdma_status(ap);
|
|
|
|
ata_ehi_push_desc(&ehc->i, "BMDMA stat 0x%x", host_stat);
|
|
|
|
/* BMDMA controllers indicate host bus error by
|
|
* setting DMA_ERR bit and timing out. As it wasn't
|
|
* really a timeout event, adjust error mask and
|
|
* cancel frozen state.
|
|
*/
|
|
if (qc->err_mask == AC_ERR_TIMEOUT && host_stat & ATA_DMA_ERR) {
|
|
qc->err_mask = AC_ERR_HOST_BUS;
|
|
thaw = 1;
|
|
}
|
|
|
|
ap->ops->bmdma_stop(qc);
|
|
}
|
|
|
|
ata_altstatus(ap);
|
|
ata_chk_status(ap);
|
|
ap->ops->irq_clear(ap);
|
|
|
|
spin_unlock_irqrestore(ap->lock, flags);
|
|
|
|
if (thaw)
|
|
ata_eh_thaw_port(ap);
|
|
|
|
/* PIO and DMA engines have been stopped, perform recovery */
|
|
ata_do_eh(ap, prereset, softreset, hardreset, postreset);
|
|
}
|
|
|
|
/**
|
|
* ata_bmdma_error_handler - Stock error handler for BMDMA controller
|
|
* @ap: port to handle error for
|
|
*
|
|
* Stock error handler for BMDMA controller.
|
|
*
|
|
* LOCKING:
|
|
* Kernel thread context (may sleep)
|
|
*/
|
|
void ata_bmdma_error_handler(struct ata_port *ap)
|
|
{
|
|
ata_reset_fn_t hardreset;
|
|
|
|
hardreset = NULL;
|
|
if (sata_scr_valid(ap))
|
|
hardreset = sata_std_hardreset;
|
|
|
|
ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
|
|
ata_std_postreset);
|
|
}
|
|
|
|
/**
|
|
* ata_bmdma_post_internal_cmd - Stock post_internal_cmd for
|
|
* BMDMA controller
|
|
* @qc: internal command to clean up
|
|
*
|
|
* LOCKING:
|
|
* Kernel thread context (may sleep)
|
|
*/
|
|
void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc)
|
|
{
|
|
ata_bmdma_stop(qc);
|
|
}
|
|
|
|
#ifdef CONFIG_PCI
|
|
/**
|
|
* ata_pci_init_native_mode - Initialize native-mode driver
|
|
* @pdev: pci device to be initialized
|
|
* @port: array[2] of pointers to port info structures.
|
|
* @ports: bitmap of ports present
|
|
*
|
|
* Utility function which allocates and initializes an
|
|
* ata_probe_ent structure for a standard dual-port
|
|
* PIO-based IDE controller. The returned ata_probe_ent
|
|
* structure can be passed to ata_device_add(). The returned
|
|
* ata_probe_ent structure should then be freed with kfree().
|
|
*
|
|
* The caller need only pass the address of the primary port, the
|
|
* secondary will be deduced automatically. If the device has non
|
|
* standard secondary port mappings this function can be called twice,
|
|
* once for each interface.
|
|
*/
|
|
|
|
struct ata_probe_ent *
|
|
ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port, int ports)
|
|
{
|
|
struct ata_probe_ent *probe_ent =
|
|
ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]);
|
|
int p = 0;
|
|
unsigned long bmdma;
|
|
|
|
if (!probe_ent)
|
|
return NULL;
|
|
|
|
probe_ent->irq = pdev->irq;
|
|
probe_ent->irq_flags = IRQF_SHARED;
|
|
probe_ent->private_data = port[0]->private_data;
|
|
|
|
if (ports & ATA_PORT_PRIMARY) {
|
|
probe_ent->port[p].cmd_addr = pci_resource_start(pdev, 0);
|
|
probe_ent->port[p].altstatus_addr =
|
|
probe_ent->port[p].ctl_addr =
|
|
pci_resource_start(pdev, 1) | ATA_PCI_CTL_OFS;
|
|
bmdma = pci_resource_start(pdev, 4);
|
|
if (bmdma) {
|
|
if (inb(bmdma + 2) & 0x80)
|
|
probe_ent->host_set_flags |= ATA_HOST_SIMPLEX;
|
|
probe_ent->port[p].bmdma_addr = bmdma;
|
|
}
|
|
ata_std_ports(&probe_ent->port[p]);
|
|
p++;
|
|
}
|
|
|
|
if (ports & ATA_PORT_SECONDARY) {
|
|
probe_ent->port[p].cmd_addr = pci_resource_start(pdev, 2);
|
|
probe_ent->port[p].altstatus_addr =
|
|
probe_ent->port[p].ctl_addr =
|
|
pci_resource_start(pdev, 3) | ATA_PCI_CTL_OFS;
|
|
bmdma = pci_resource_start(pdev, 4);
|
|
if (bmdma) {
|
|
bmdma += 8;
|
|
if(inb(bmdma + 2) & 0x80)
|
|
probe_ent->host_set_flags |= ATA_HOST_SIMPLEX;
|
|
probe_ent->port[p].bmdma_addr = bmdma;
|
|
}
|
|
ata_std_ports(&probe_ent->port[p]);
|
|
p++;
|
|
}
|
|
|
|
probe_ent->n_ports = p;
|
|
return probe_ent;
|
|
}
|
|
|
|
|
|
static struct ata_probe_ent *ata_pci_init_legacy_port(struct pci_dev *pdev,
|
|
struct ata_port_info **port, int port_mask)
|
|
{
|
|
struct ata_probe_ent *probe_ent;
|
|
unsigned long bmdma = pci_resource_start(pdev, 4);
|
|
|
|
probe_ent = ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]);
|
|
if (!probe_ent)
|
|
return NULL;
|
|
|
|
probe_ent->n_ports = 2;
|
|
probe_ent->private_data = port[0]->private_data;
|
|
|
|
if (port_mask & ATA_PORT_PRIMARY) {
|
|
probe_ent->irq = 14;
|
|
probe_ent->port[0].cmd_addr = ATA_PRIMARY_CMD;
|
|
probe_ent->port[0].altstatus_addr =
|
|
probe_ent->port[0].ctl_addr = ATA_PRIMARY_CTL;
|
|
if (bmdma) {
|
|
probe_ent->port[0].bmdma_addr = bmdma;
|
|
if (inb(bmdma + 2) & 0x80)
|
|
probe_ent->host_set_flags |= ATA_HOST_SIMPLEX;
|
|
}
|
|
ata_std_ports(&probe_ent->port[0]);
|
|
} else
|
|
probe_ent->dummy_port_mask |= ATA_PORT_PRIMARY;
|
|
|
|
if (port_mask & ATA_PORT_SECONDARY) {
|
|
if (probe_ent->irq)
|
|
probe_ent->irq2 = 15;
|
|
else
|
|
probe_ent->irq = 15;
|
|
probe_ent->port[1].cmd_addr = ATA_SECONDARY_CMD;
|
|
probe_ent->port[1].altstatus_addr =
|
|
probe_ent->port[1].ctl_addr = ATA_SECONDARY_CTL;
|
|
if (bmdma) {
|
|
probe_ent->port[1].bmdma_addr = bmdma + 8;
|
|
if (inb(bmdma + 10) & 0x80)
|
|
probe_ent->host_set_flags |= ATA_HOST_SIMPLEX;
|
|
}
|
|
ata_std_ports(&probe_ent->port[1]);
|
|
} else
|
|
probe_ent->dummy_port_mask |= ATA_PORT_SECONDARY;
|
|
|
|
return probe_ent;
|
|
}
|
|
|
|
|
|
/**
|
|
* ata_pci_init_one - Initialize/register PCI IDE host controller
|
|
* @pdev: Controller to be initialized
|
|
* @port_info: Information from low-level host driver
|
|
* @n_ports: Number of ports attached to host controller
|
|
*
|
|
* This is a helper function which can be called from a driver's
|
|
* xxx_init_one() probe function if the hardware uses traditional
|
|
* IDE taskfile registers.
|
|
*
|
|
* This function calls pci_enable_device(), reserves its register
|
|
* regions, sets the dma mask, enables bus master mode, and calls
|
|
* ata_device_add()
|
|
*
|
|
* ASSUMPTION:
|
|
* Nobody makes a single channel controller that appears solely as
|
|
* the secondary legacy port on PCI.
|
|
*
|
|
* LOCKING:
|
|
* Inherited from PCI layer (may sleep).
|
|
*
|
|
* RETURNS:
|
|
* Zero on success, negative on errno-based value on error.
|
|
*/
|
|
|
|
int ata_pci_init_one (struct pci_dev *pdev, struct ata_port_info **port_info,
|
|
unsigned int n_ports)
|
|
{
|
|
struct ata_probe_ent *probe_ent = NULL;
|
|
struct ata_port_info *port[2];
|
|
u8 tmp8, mask;
|
|
unsigned int legacy_mode = 0;
|
|
int disable_dev_on_err = 1;
|
|
int rc;
|
|
|
|
DPRINTK("ENTER\n");
|
|
|
|
port[0] = port_info[0];
|
|
if (n_ports > 1)
|
|
port[1] = port_info[1];
|
|
else
|
|
port[1] = port[0];
|
|
|
|
if ((port[0]->host_flags & ATA_FLAG_NO_LEGACY) == 0
|
|
&& (pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
|
|
/* TODO: What if one channel is in native mode ... */
|
|
pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
|
|
mask = (1 << 2) | (1 << 0);
|
|
if ((tmp8 & mask) != mask)
|
|
legacy_mode = (1 << 3);
|
|
}
|
|
|
|
/* FIXME... */
|
|
if ((!legacy_mode) && (n_ports > 2)) {
|
|
printk(KERN_ERR "ata: BUG: native mode, n_ports > 2\n");
|
|
n_ports = 2;
|
|
/* For now */
|
|
}
|
|
|
|
/* FIXME: Really for ATA it isn't safe because the device may be
|
|
multi-purpose and we want to leave it alone if it was already
|
|
enabled. Secondly for shared use as Arjan says we want refcounting
|
|
|
|
Checking dev->is_enabled is insufficient as this is not set at
|
|
boot for the primary video which is BIOS enabled
|
|
*/
|
|
|
|
rc = pci_enable_device(pdev);
|
|
if (rc)
|
|
return rc;
|
|
|
|
rc = pci_request_regions(pdev, DRV_NAME);
|
|
if (rc) {
|
|
disable_dev_on_err = 0;
|
|
goto err_out;
|
|
}
|
|
|
|
if (legacy_mode) {
|
|
if (!request_region(ATA_PRIMARY_CMD, 8, "libata")) {
|
|
struct resource *conflict, res;
|
|
res.start = ATA_PRIMARY_CMD;
|
|
res.end = ATA_PRIMARY_CMD + 8 - 1;
|
|
conflict = ____request_resource(&ioport_resource, &res);
|
|
if (!strcmp(conflict->name, "libata"))
|
|
legacy_mode |= ATA_PORT_PRIMARY;
|
|
else {
|
|
disable_dev_on_err = 0;
|
|
printk(KERN_WARNING "ata: 0x%0X IDE port busy\n", ATA_PRIMARY_CMD);
|
|
}
|
|
} else
|
|
legacy_mode |= ATA_PORT_PRIMARY;
|
|
|
|
if (!request_region(ATA_SECONDARY_CMD, 8, "libata")) {
|
|
struct resource *conflict, res;
|
|
res.start = ATA_SECONDARY_CMD;
|
|
res.end = ATA_SECONDARY_CMD + 8 - 1;
|
|
conflict = ____request_resource(&ioport_resource, &res);
|
|
if (!strcmp(conflict->name, "libata"))
|
|
legacy_mode |= ATA_PORT_SECONDARY;
|
|
else {
|
|
disable_dev_on_err = 0;
|
|
printk(KERN_WARNING "ata: 0x%X IDE port busy\n", ATA_SECONDARY_CMD);
|
|
}
|
|
} else
|
|
legacy_mode |= ATA_PORT_SECONDARY;
|
|
}
|
|
|
|
/* we have legacy mode, but all ports are unavailable */
|
|
if (legacy_mode == (1 << 3)) {
|
|
rc = -EBUSY;
|
|
goto err_out_regions;
|
|
}
|
|
|
|
/* FIXME: If we get no DMA mask we should fall back to PIO */
|
|
rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
|
|
if (rc)
|
|
goto err_out_regions;
|
|
rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
|
|
if (rc)
|
|
goto err_out_regions;
|
|
|
|
if (legacy_mode) {
|
|
probe_ent = ata_pci_init_legacy_port(pdev, port, legacy_mode);
|
|
} else {
|
|
if (n_ports == 2)
|
|
probe_ent = ata_pci_init_native_mode(pdev, port, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
|
|
else
|
|
probe_ent = ata_pci_init_native_mode(pdev, port, ATA_PORT_PRIMARY);
|
|
}
|
|
if (!probe_ent) {
|
|
rc = -ENOMEM;
|
|
goto err_out_regions;
|
|
}
|
|
|
|
pci_set_master(pdev);
|
|
|
|
/* FIXME: check ata_device_add return */
|
|
ata_device_add(probe_ent);
|
|
|
|
kfree(probe_ent);
|
|
|
|
return 0;
|
|
|
|
err_out_regions:
|
|
if (legacy_mode & ATA_PORT_PRIMARY)
|
|
release_region(ATA_PRIMARY_CMD, 8);
|
|
if (legacy_mode & ATA_PORT_SECONDARY)
|
|
release_region(ATA_SECONDARY_CMD, 8);
|
|
pci_release_regions(pdev);
|
|
err_out:
|
|
if (disable_dev_on_err)
|
|
pci_disable_device(pdev);
|
|
return rc;
|
|
}
|
|
|
|
/**
|
|
* ata_pci_clear_simplex - attempt to kick device out of simplex
|
|
* @pdev: PCI device
|
|
*
|
|
* Some PCI ATA devices report simplex mode but in fact can be told to
|
|
* enter non simplex mode. This implements the neccessary logic to
|
|
* perform the task on such devices. Calling it on other devices will
|
|
* have -undefined- behaviour.
|
|
*/
|
|
|
|
int ata_pci_clear_simplex(struct pci_dev *pdev)
|
|
{
|
|
unsigned long bmdma = pci_resource_start(pdev, 4);
|
|
u8 simplex;
|
|
|
|
if (bmdma == 0)
|
|
return -ENOENT;
|
|
|
|
simplex = inb(bmdma + 0x02);
|
|
outb(simplex & 0x60, bmdma + 0x02);
|
|
simplex = inb(bmdma + 0x02);
|
|
if (simplex & 0x80)
|
|
return -EOPNOTSUPP;
|
|
return 0;
|
|
}
|
|
|
|
unsigned long ata_pci_default_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long xfer_mask)
|
|
{
|
|
/* Filter out DMA modes if the device has been configured by
|
|
the BIOS as PIO only */
|
|
|
|
if (ap->ioaddr.bmdma_addr == 0)
|
|
xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
|
|
return xfer_mask;
|
|
}
|
|
|
|
#endif /* CONFIG_PCI */
|
|
|