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ac2c55e226
Add a compatible string for Nuvoton BMC NPCM845 PSPI. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20220722114136.251415-2-tmaimon77@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
36 lines
1.3 KiB
Text
36 lines
1.3 KiB
Text
Nuvoton NPCM Peripheral Serial Peripheral Interface(PSPI) controller driver
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Nuvoton NPCM7xx SOC support two PSPI channels.
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Required properties:
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- compatible : "nuvoton,npcm750-pspi" for Poleg NPCM7XX.
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"nuvoton,npcm845-pspi" for Arbel NPCM8XX.
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- #address-cells : should be 1. see spi-bus.txt
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- #size-cells : should be 0. see spi-bus.txt
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- specifies physical base address and size of the register.
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- interrupts : contain PSPI interrupt.
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- clocks : phandle of PSPI reference clock.
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- clock-names: Should be "clk_apb5".
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- pinctrl-names : a pinctrl state named "default" must be defined.
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- pinctrl-0 : phandle referencing pin configuration of the device.
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- resets : phandle to the reset control for this device.
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- cs-gpios: Specifies the gpio pins to be used for chipselects.
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See: Documentation/devicetree/bindings/spi/spi-bus.txt
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Optional properties:
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- clock-frequency : Input clock frequency to the PSPI block in Hz.
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Default is 25000000 Hz.
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spi0: spi@f0200000 {
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compatible = "nuvoton,npcm750-pspi";
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reg = <0xf0200000 0x1000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pspi1_pins>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk NPCM7XX_CLK_APB5>;
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clock-names = "clk_apb5";
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resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>
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cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
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};
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