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81432e2e51
Add a configurable clock base rate for the pwm as when being built for non-PCI the block may be sourced from an internal clock. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230907161242.67190-3-ben.dooks@codethink.co.uk Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
60 lines
1.5 KiB
C
60 lines
1.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* DesignWare PWM Controller driver
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*
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* Copyright (C) 2018-2020 Intel Corporation
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*
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* Author: Felipe Balbi (Intel)
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* Author: Jarkko Nikula <jarkko.nikula@linux.intel.com>
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* Author: Raymond Tan <raymond.tan@intel.com>
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*/
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MODULE_IMPORT_NS(dwc_pwm);
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#define DWC_TIM_LD_CNT(n) ((n) * 0x14)
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#define DWC_TIM_LD_CNT2(n) (((n) * 4) + 0xb0)
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#define DWC_TIM_CUR_VAL(n) (((n) * 0x14) + 0x04)
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#define DWC_TIM_CTRL(n) (((n) * 0x14) + 0x08)
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#define DWC_TIM_EOI(n) (((n) * 0x14) + 0x0c)
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#define DWC_TIM_INT_STS(n) (((n) * 0x14) + 0x10)
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#define DWC_TIMERS_INT_STS 0xa0
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#define DWC_TIMERS_EOI 0xa4
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#define DWC_TIMERS_RAW_INT_STS 0xa8
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#define DWC_TIMERS_COMP_VERSION 0xac
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#define DWC_TIMERS_TOTAL 8
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/* Timer Control Register */
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#define DWC_TIM_CTRL_EN BIT(0)
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#define DWC_TIM_CTRL_MODE BIT(1)
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#define DWC_TIM_CTRL_MODE_FREE (0 << 1)
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#define DWC_TIM_CTRL_MODE_USER (1 << 1)
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#define DWC_TIM_CTRL_INT_MASK BIT(2)
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#define DWC_TIM_CTRL_PWM BIT(3)
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struct dwc_pwm_ctx {
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u32 cnt;
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u32 cnt2;
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u32 ctrl;
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};
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struct dwc_pwm {
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struct pwm_chip chip;
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void __iomem *base;
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unsigned int clk_ns;
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struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL];
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};
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#define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip))
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static inline u32 dwc_pwm_readl(struct dwc_pwm *dwc, u32 offset)
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{
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return readl(dwc->base + offset);
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}
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static inline void dwc_pwm_writel(struct dwc_pwm *dwc, u32 value, u32 offset)
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{
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writel(value, dwc->base + offset);
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}
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extern struct dwc_pwm *dwc_pwm_alloc(struct device *dev);
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