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![Alexander Shishkin](/assets/img/avatar_default.png)
Some devices don't drain their pipelines if we don't make sure that the corresponding output port is in reset before programming it for a new trace capture, resulting in bits of old trace appearing in the new trace capture. Fix that by explicitly making sure the reset is asserted before programming new trace capture. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Link: https://lore.kernel.org/r/20210621151246.31891-5-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
850 lines
21 KiB
C
850 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Intel(R) Trace Hub Global Trace Hub
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*
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* Copyright (C) 2014-2015 Intel Corporation.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include <linux/bitmap.h>
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#include <linux/pm_runtime.h>
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#include "intel_th.h"
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#include "gth.h"
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struct gth_device;
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/**
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* struct gth_output - GTH view on an output port
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* @gth: backlink to the GTH device
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* @output: link to output device's output descriptor
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* @index: output port number
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* @port_type: one of GTH_* port type values
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* @master: bitmap of masters configured for this output
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*/
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struct gth_output {
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struct gth_device *gth;
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struct intel_th_output *output;
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unsigned int index;
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unsigned int port_type;
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DECLARE_BITMAP(master, TH_CONFIGURABLE_MASTERS + 1);
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};
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/**
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* struct gth_device - GTH device
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* @dev: driver core's device
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* @base: register window base address
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* @output_group: attributes describing output ports
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* @master_group: attributes describing master assignments
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* @output: output ports
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* @master: master/output port assignments
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* @gth_lock: serializes accesses to GTH bits
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*/
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struct gth_device {
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struct device *dev;
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void __iomem *base;
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struct attribute_group output_group;
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struct attribute_group master_group;
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struct gth_output output[TH_POSSIBLE_OUTPUTS];
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signed char master[TH_CONFIGURABLE_MASTERS + 1];
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spinlock_t gth_lock;
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};
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static void gth_output_set(struct gth_device *gth, int port,
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unsigned int config)
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{
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unsigned long reg = port & 4 ? REG_GTH_GTHOPT1 : REG_GTH_GTHOPT0;
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u32 val;
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int shift = (port & 3) * 8;
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val = ioread32(gth->base + reg);
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val &= ~(0xff << shift);
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val |= config << shift;
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iowrite32(val, gth->base + reg);
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}
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static unsigned int gth_output_get(struct gth_device *gth, int port)
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{
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unsigned long reg = port & 4 ? REG_GTH_GTHOPT1 : REG_GTH_GTHOPT0;
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u32 val;
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int shift = (port & 3) * 8;
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val = ioread32(gth->base + reg);
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val &= 0xff << shift;
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val >>= shift;
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return val;
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}
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static void gth_smcfreq_set(struct gth_device *gth, int port,
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unsigned int freq)
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{
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unsigned long reg = REG_GTH_SMCR0 + ((port / 2) * 4);
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int shift = (port & 1) * 16;
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u32 val;
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val = ioread32(gth->base + reg);
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val &= ~(0xffff << shift);
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val |= freq << shift;
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iowrite32(val, gth->base + reg);
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}
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static unsigned int gth_smcfreq_get(struct gth_device *gth, int port)
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{
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unsigned long reg = REG_GTH_SMCR0 + ((port / 2) * 4);
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int shift = (port & 1) * 16;
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u32 val;
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val = ioread32(gth->base + reg);
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val &= 0xffff << shift;
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val >>= shift;
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return val;
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}
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/*
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* "masters" attribute group
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*/
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struct master_attribute {
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struct device_attribute attr;
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struct gth_device *gth;
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unsigned int master;
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};
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static void
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gth_master_set(struct gth_device *gth, unsigned int master, int port)
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{
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unsigned int reg = REG_GTH_SWDEST0 + ((master >> 1) & ~3u);
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unsigned int shift = (master & 0x7) * 4;
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u32 val;
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if (master >= 256) {
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reg = REG_GTH_GSWTDEST;
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shift = 0;
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}
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val = ioread32(gth->base + reg);
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val &= ~(0xf << shift);
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if (port >= 0)
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val |= (0x8 | port) << shift;
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iowrite32(val, gth->base + reg);
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}
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static ssize_t master_attr_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct master_attribute *ma =
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container_of(attr, struct master_attribute, attr);
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struct gth_device *gth = ma->gth;
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size_t count;
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int port;
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spin_lock(>h->gth_lock);
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port = gth->master[ma->master];
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spin_unlock(>h->gth_lock);
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if (port >= 0)
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count = snprintf(buf, PAGE_SIZE, "%x\n", port);
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else
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count = snprintf(buf, PAGE_SIZE, "disabled\n");
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return count;
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}
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static ssize_t master_attr_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct master_attribute *ma =
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container_of(attr, struct master_attribute, attr);
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struct gth_device *gth = ma->gth;
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int old_port, port;
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if (kstrtoint(buf, 10, &port) < 0)
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return -EINVAL;
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if (port >= TH_POSSIBLE_OUTPUTS || port < -1)
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return -EINVAL;
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spin_lock(>h->gth_lock);
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/* disconnect from the previous output port, if any */
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old_port = gth->master[ma->master];
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if (old_port >= 0) {
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gth->master[ma->master] = -1;
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clear_bit(ma->master, gth->output[old_port].master);
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/*
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* if the port is active, program this setting,
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* implies that runtime PM is on
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*/
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if (gth->output[old_port].output->active)
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gth_master_set(gth, ma->master, -1);
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}
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/* connect to the new output port, if any */
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if (port >= 0) {
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/* check if there's a driver for this port */
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if (!gth->output[port].output) {
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count = -ENODEV;
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goto unlock;
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}
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set_bit(ma->master, gth->output[port].master);
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/* if the port is active, program this setting, see above */
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if (gth->output[port].output->active)
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gth_master_set(gth, ma->master, port);
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}
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gth->master[ma->master] = port;
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unlock:
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spin_unlock(>h->gth_lock);
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return count;
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}
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struct output_attribute {
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struct device_attribute attr;
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struct gth_device *gth;
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unsigned int port;
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unsigned int parm;
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};
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#define OUTPUT_PARM(_name, _mask, _r, _w, _what) \
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[TH_OUTPUT_PARM(_name)] = { .name = __stringify(_name), \
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.get = gth_ ## _what ## _get, \
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.set = gth_ ## _what ## _set, \
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.mask = (_mask), \
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.readable = (_r), \
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.writable = (_w) }
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static const struct output_parm {
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const char *name;
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unsigned int (*get)(struct gth_device *gth, int port);
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void (*set)(struct gth_device *gth, int port,
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unsigned int val);
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unsigned int mask;
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unsigned int readable : 1,
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writable : 1;
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} output_parms[] = {
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OUTPUT_PARM(port, 0x7, 1, 0, output),
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OUTPUT_PARM(null, BIT(3), 1, 1, output),
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OUTPUT_PARM(drop, BIT(4), 1, 1, output),
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OUTPUT_PARM(reset, BIT(5), 1, 0, output),
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OUTPUT_PARM(flush, BIT(7), 0, 1, output),
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OUTPUT_PARM(smcfreq, 0xffff, 1, 1, smcfreq),
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};
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static void
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gth_output_parm_set(struct gth_device *gth, int port, unsigned int parm,
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unsigned int val)
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{
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unsigned int config = output_parms[parm].get(gth, port);
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unsigned int mask = output_parms[parm].mask;
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unsigned int shift = __ffs(mask);
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config &= ~mask;
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config |= (val << shift) & mask;
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output_parms[parm].set(gth, port, config);
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}
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static unsigned int
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gth_output_parm_get(struct gth_device *gth, int port, unsigned int parm)
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{
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unsigned int config = output_parms[parm].get(gth, port);
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unsigned int mask = output_parms[parm].mask;
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unsigned int shift = __ffs(mask);
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config &= mask;
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config >>= shift;
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return config;
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}
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/*
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* Reset outputs and sources
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*/
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static int intel_th_gth_reset(struct gth_device *gth)
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{
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u32 reg;
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int port, i;
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reg = ioread32(gth->base + REG_GTH_SCRPD0);
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if (reg & SCRPD_DEBUGGER_IN_USE)
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return -EBUSY;
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/* Always save/restore STH and TU registers in S0ix entry/exit */
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reg |= SCRPD_STH_IS_ENABLED | SCRPD_TRIGGER_IS_ENABLED;
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iowrite32(reg, gth->base + REG_GTH_SCRPD0);
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/* output ports */
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for (port = 0; port < 8; port++) {
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if (gth_output_parm_get(gth, port, TH_OUTPUT_PARM(port)) ==
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GTH_NONE)
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continue;
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gth_output_set(gth, port, 0);
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gth_smcfreq_set(gth, port, 16);
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}
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/* disable overrides */
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iowrite32(0, gth->base + REG_GTH_DESTOVR);
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/* masters swdest_0~31 and gswdest */
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for (i = 0; i < 33; i++)
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iowrite32(0, gth->base + REG_GTH_SWDEST0 + i * 4);
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/* sources */
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iowrite32(0, gth->base + REG_GTH_SCR);
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iowrite32(0xfc, gth->base + REG_GTH_SCR2);
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/* setup CTS for single trigger */
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iowrite32(CTS_EVENT_ENABLE_IF_ANYTHING, gth->base + REG_CTS_C0S0_EN);
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iowrite32(CTS_ACTION_CONTROL_SET_STATE(CTS_STATE_IDLE) |
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CTS_ACTION_CONTROL_TRIGGER, gth->base + REG_CTS_C0S0_ACT);
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return 0;
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}
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/*
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* "outputs" attribute group
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*/
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static ssize_t output_attr_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct output_attribute *oa =
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container_of(attr, struct output_attribute, attr);
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struct gth_device *gth = oa->gth;
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size_t count;
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pm_runtime_get_sync(dev);
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spin_lock(>h->gth_lock);
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count = snprintf(buf, PAGE_SIZE, "%x\n",
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gth_output_parm_get(gth, oa->port, oa->parm));
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spin_unlock(>h->gth_lock);
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pm_runtime_put(dev);
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return count;
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}
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static ssize_t output_attr_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct output_attribute *oa =
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container_of(attr, struct output_attribute, attr);
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struct gth_device *gth = oa->gth;
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unsigned int config;
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if (kstrtouint(buf, 16, &config) < 0)
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return -EINVAL;
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pm_runtime_get_sync(dev);
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spin_lock(>h->gth_lock);
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gth_output_parm_set(gth, oa->port, oa->parm, config);
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spin_unlock(>h->gth_lock);
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pm_runtime_put(dev);
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return count;
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}
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static int intel_th_master_attributes(struct gth_device *gth)
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{
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struct master_attribute *master_attrs;
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struct attribute **attrs;
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int i, nattrs = TH_CONFIGURABLE_MASTERS + 2;
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attrs = devm_kcalloc(gth->dev, nattrs, sizeof(void *), GFP_KERNEL);
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if (!attrs)
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return -ENOMEM;
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master_attrs = devm_kcalloc(gth->dev, nattrs,
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sizeof(struct master_attribute),
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GFP_KERNEL);
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if (!master_attrs)
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return -ENOMEM;
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for (i = 0; i < TH_CONFIGURABLE_MASTERS + 1; i++) {
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char *name;
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name = devm_kasprintf(gth->dev, GFP_KERNEL, "%d%s", i,
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i == TH_CONFIGURABLE_MASTERS ? "+" : "");
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if (!name)
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return -ENOMEM;
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master_attrs[i].attr.attr.name = name;
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master_attrs[i].attr.attr.mode = S_IRUGO | S_IWUSR;
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master_attrs[i].attr.show = master_attr_show;
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master_attrs[i].attr.store = master_attr_store;
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sysfs_attr_init(&master_attrs[i].attr.attr);
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attrs[i] = &master_attrs[i].attr.attr;
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master_attrs[i].gth = gth;
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master_attrs[i].master = i;
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}
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gth->master_group.name = "masters";
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gth->master_group.attrs = attrs;
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return sysfs_create_group(>h->dev->kobj, >h->master_group);
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}
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static int intel_th_output_attributes(struct gth_device *gth)
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{
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struct output_attribute *out_attrs;
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struct attribute **attrs;
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int i, j, nouts = TH_POSSIBLE_OUTPUTS;
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int nparms = ARRAY_SIZE(output_parms);
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int nattrs = nouts * nparms + 1;
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attrs = devm_kcalloc(gth->dev, nattrs, sizeof(void *), GFP_KERNEL);
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if (!attrs)
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return -ENOMEM;
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out_attrs = devm_kcalloc(gth->dev, nattrs,
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sizeof(struct output_attribute),
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GFP_KERNEL);
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if (!out_attrs)
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return -ENOMEM;
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for (i = 0; i < nouts; i++) {
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for (j = 0; j < nparms; j++) {
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unsigned int idx = i * nparms + j;
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char *name;
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name = devm_kasprintf(gth->dev, GFP_KERNEL, "%d_%s", i,
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output_parms[j].name);
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if (!name)
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return -ENOMEM;
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out_attrs[idx].attr.attr.name = name;
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if (output_parms[j].readable) {
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out_attrs[idx].attr.attr.mode |= S_IRUGO;
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out_attrs[idx].attr.show = output_attr_show;
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}
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if (output_parms[j].writable) {
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out_attrs[idx].attr.attr.mode |= S_IWUSR;
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out_attrs[idx].attr.store = output_attr_store;
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}
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sysfs_attr_init(&out_attrs[idx].attr.attr);
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attrs[idx] = &out_attrs[idx].attr.attr;
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out_attrs[idx].gth = gth;
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out_attrs[idx].port = i;
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out_attrs[idx].parm = j;
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}
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}
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gth->output_group.name = "outputs";
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gth->output_group.attrs = attrs;
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return sysfs_create_group(>h->dev->kobj, >h->output_group);
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}
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/**
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* intel_th_gth_stop() - stop tracing to an output device
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* @gth: GTH device
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* @output: output device's descriptor
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* @capture_done: set when no more traces will be captured
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*
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* This will stop tracing using force storeEn off signal and wait for the
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* pipelines to be empty for the corresponding output port.
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*/
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static void intel_th_gth_stop(struct gth_device *gth,
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struct intel_th_output *output,
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bool capture_done)
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{
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struct intel_th_device *outdev =
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container_of(output, struct intel_th_device, output);
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struct intel_th_driver *outdrv =
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to_intel_th_driver(outdev->dev.driver);
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unsigned long count;
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u32 reg;
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u32 scr2 = 0xfc | (capture_done ? 1 : 0);
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iowrite32(0, gth->base + REG_GTH_SCR);
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iowrite32(scr2, gth->base + REG_GTH_SCR2);
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/* wait on pipeline empty for the given port */
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for (reg = 0, count = GTH_PLE_WAITLOOP_DEPTH;
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count && !(reg & BIT(output->port)); count--) {
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reg = ioread32(gth->base + REG_GTH_STAT);
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cpu_relax();
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}
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if (!count)
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dev_dbg(gth->dev, "timeout waiting for GTH[%d] PLE\n",
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output->port);
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/* wait on output piepline empty */
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if (outdrv->wait_empty)
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outdrv->wait_empty(outdev);
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/* clear force capture done for next captures */
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iowrite32(0xfc, gth->base + REG_GTH_SCR2);
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}
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|
/**
|
|
* intel_th_gth_start() - start tracing to an output device
|
|
* @gth: GTH device
|
|
* @output: output device's descriptor
|
|
*
|
|
* This will start tracing using force storeEn signal.
|
|
*/
|
|
static void intel_th_gth_start(struct gth_device *gth,
|
|
struct intel_th_output *output)
|
|
{
|
|
u32 scr = 0xfc0000;
|
|
|
|
if (output->multiblock)
|
|
scr |= 0xff;
|
|
|
|
iowrite32(scr, gth->base + REG_GTH_SCR);
|
|
iowrite32(0, gth->base + REG_GTH_SCR2);
|
|
}
|
|
|
|
/**
|
|
* intel_th_gth_disable() - disable tracing to an output device
|
|
* @thdev: GTH device
|
|
* @output: output device's descriptor
|
|
*
|
|
* This will deconfigure all masters set to output to this device,
|
|
* disable tracing using force storeEn off signal and wait for the
|
|
* "pipeline empty" bit for corresponding output port.
|
|
*/
|
|
static void intel_th_gth_disable(struct intel_th_device *thdev,
|
|
struct intel_th_output *output)
|
|
{
|
|
struct gth_device *gth = dev_get_drvdata(&thdev->dev);
|
|
int master;
|
|
u32 reg;
|
|
|
|
spin_lock(>h->gth_lock);
|
|
output->active = false;
|
|
|
|
for_each_set_bit(master, gth->output[output->port].master,
|
|
TH_CONFIGURABLE_MASTERS + 1) {
|
|
gth_master_set(gth, master, -1);
|
|
}
|
|
spin_unlock(>h->gth_lock);
|
|
|
|
intel_th_gth_stop(gth, output, true);
|
|
|
|
reg = ioread32(gth->base + REG_GTH_SCRPD0);
|
|
reg &= ~output->scratchpad;
|
|
iowrite32(reg, gth->base + REG_GTH_SCRPD0);
|
|
}
|
|
|
|
static void gth_tscu_resync(struct gth_device *gth)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = ioread32(gth->base + REG_TSCU_TSUCTRL);
|
|
reg &= ~TSUCTRL_CTCRESYNC;
|
|
iowrite32(reg, gth->base + REG_TSCU_TSUCTRL);
|
|
}
|
|
|
|
static void intel_th_gth_prepare(struct intel_th_device *thdev,
|
|
struct intel_th_output *output)
|
|
{
|
|
struct gth_device *gth = dev_get_drvdata(&thdev->dev);
|
|
int count;
|
|
|
|
/*
|
|
* Wait until the output port is in reset before we start
|
|
* programming it.
|
|
*/
|
|
for (count = GTH_PLE_WAITLOOP_DEPTH;
|
|
count && !(gth_output_get(gth, output->port) & BIT(5)); count--)
|
|
cpu_relax();
|
|
}
|
|
|
|
/**
|
|
* intel_th_gth_enable() - enable tracing to an output device
|
|
* @thdev: GTH device
|
|
* @output: output device's descriptor
|
|
*
|
|
* This will configure all masters set to output to this device and
|
|
* enable tracing using force storeEn signal.
|
|
*/
|
|
static void intel_th_gth_enable(struct intel_th_device *thdev,
|
|
struct intel_th_output *output)
|
|
{
|
|
struct gth_device *gth = dev_get_drvdata(&thdev->dev);
|
|
struct intel_th *th = to_intel_th(thdev);
|
|
int master;
|
|
u32 scrpd;
|
|
|
|
spin_lock(>h->gth_lock);
|
|
for_each_set_bit(master, gth->output[output->port].master,
|
|
TH_CONFIGURABLE_MASTERS + 1) {
|
|
gth_master_set(gth, master, output->port);
|
|
}
|
|
|
|
output->active = true;
|
|
spin_unlock(>h->gth_lock);
|
|
|
|
if (INTEL_TH_CAP(th, tscu_enable))
|
|
gth_tscu_resync(gth);
|
|
|
|
scrpd = ioread32(gth->base + REG_GTH_SCRPD0);
|
|
scrpd |= output->scratchpad;
|
|
iowrite32(scrpd, gth->base + REG_GTH_SCRPD0);
|
|
|
|
intel_th_gth_start(gth, output);
|
|
}
|
|
|
|
/**
|
|
* intel_th_gth_switch() - execute a switch sequence
|
|
* @thdev: GTH device
|
|
* @output: output device's descriptor
|
|
*
|
|
* This will execute a switch sequence that will trigger a switch window
|
|
* when tracing to MSC in multi-block mode.
|
|
*/
|
|
static void intel_th_gth_switch(struct intel_th_device *thdev,
|
|
struct intel_th_output *output)
|
|
{
|
|
struct gth_device *gth = dev_get_drvdata(&thdev->dev);
|
|
unsigned long count;
|
|
u32 reg;
|
|
|
|
/* trigger */
|
|
iowrite32(0, gth->base + REG_CTS_CTL);
|
|
iowrite32(CTS_CTL_SEQUENCER_ENABLE, gth->base + REG_CTS_CTL);
|
|
/* wait on trigger status */
|
|
for (reg = 0, count = CTS_TRIG_WAITLOOP_DEPTH;
|
|
count && !(reg & BIT(4)); count--) {
|
|
reg = ioread32(gth->base + REG_CTS_STAT);
|
|
cpu_relax();
|
|
}
|
|
if (!count)
|
|
dev_dbg(&thdev->dev, "timeout waiting for CTS Trigger\n");
|
|
|
|
/* De-assert the trigger */
|
|
iowrite32(0, gth->base + REG_CTS_CTL);
|
|
|
|
intel_th_gth_stop(gth, output, false);
|
|
intel_th_gth_start(gth, output);
|
|
}
|
|
|
|
/**
|
|
* intel_th_gth_assign() - assign output device to a GTH output port
|
|
* @thdev: GTH device
|
|
* @othdev: output device
|
|
*
|
|
* This will match a given output device parameters against present
|
|
* output ports on the GTH and fill out relevant bits in output device's
|
|
* descriptor.
|
|
*
|
|
* Return: 0 on success, -errno on error.
|
|
*/
|
|
static int intel_th_gth_assign(struct intel_th_device *thdev,
|
|
struct intel_th_device *othdev)
|
|
{
|
|
struct gth_device *gth = dev_get_drvdata(&thdev->dev);
|
|
int i, id;
|
|
|
|
if (thdev->host_mode)
|
|
return -EBUSY;
|
|
|
|
if (othdev->type != INTEL_TH_OUTPUT)
|
|
return -EINVAL;
|
|
|
|
for (i = 0, id = 0; i < TH_POSSIBLE_OUTPUTS; i++) {
|
|
if (gth->output[i].port_type != othdev->output.type)
|
|
continue;
|
|
|
|
if (othdev->id == -1 || othdev->id == id)
|
|
goto found;
|
|
|
|
id++;
|
|
}
|
|
|
|
return -ENOENT;
|
|
|
|
found:
|
|
spin_lock(>h->gth_lock);
|
|
othdev->output.port = i;
|
|
othdev->output.active = false;
|
|
gth->output[i].output = &othdev->output;
|
|
spin_unlock(>h->gth_lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* intel_th_gth_unassign() - deassociate an output device from its output port
|
|
* @thdev: GTH device
|
|
* @othdev: output device
|
|
*/
|
|
static void intel_th_gth_unassign(struct intel_th_device *thdev,
|
|
struct intel_th_device *othdev)
|
|
{
|
|
struct gth_device *gth = dev_get_drvdata(&thdev->dev);
|
|
int port = othdev->output.port;
|
|
int master;
|
|
|
|
if (thdev->host_mode)
|
|
return;
|
|
|
|
spin_lock(>h->gth_lock);
|
|
othdev->output.port = -1;
|
|
othdev->output.active = false;
|
|
gth->output[port].output = NULL;
|
|
for (master = 0; master < TH_CONFIGURABLE_MASTERS + 1; master++)
|
|
if (gth->master[master] == port)
|
|
gth->master[master] = -1;
|
|
spin_unlock(>h->gth_lock);
|
|
}
|
|
|
|
static int
|
|
intel_th_gth_set_output(struct intel_th_device *thdev, unsigned int master)
|
|
{
|
|
struct gth_device *gth = dev_get_drvdata(&thdev->dev);
|
|
int port = 0; /* FIXME: make default output configurable */
|
|
|
|
/*
|
|
* everything above TH_CONFIGURABLE_MASTERS is controlled by the
|
|
* same register
|
|
*/
|
|
if (master > TH_CONFIGURABLE_MASTERS)
|
|
master = TH_CONFIGURABLE_MASTERS;
|
|
|
|
spin_lock(>h->gth_lock);
|
|
if (gth->master[master] == -1) {
|
|
set_bit(master, gth->output[port].master);
|
|
gth->master[master] = port;
|
|
}
|
|
spin_unlock(>h->gth_lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int intel_th_gth_probe(struct intel_th_device *thdev)
|
|
{
|
|
struct device *dev = &thdev->dev;
|
|
struct intel_th *th = dev_get_drvdata(dev->parent);
|
|
struct gth_device *gth;
|
|
struct resource *res;
|
|
void __iomem *base;
|
|
int i, ret;
|
|
|
|
res = intel_th_device_get_resource(thdev, IORESOURCE_MEM, 0);
|
|
if (!res)
|
|
return -ENODEV;
|
|
|
|
base = devm_ioremap(dev, res->start, resource_size(res));
|
|
if (!base)
|
|
return -ENOMEM;
|
|
|
|
gth = devm_kzalloc(dev, sizeof(*gth), GFP_KERNEL);
|
|
if (!gth)
|
|
return -ENOMEM;
|
|
|
|
gth->dev = dev;
|
|
gth->base = base;
|
|
spin_lock_init(>h->gth_lock);
|
|
|
|
dev_set_drvdata(dev, gth);
|
|
|
|
/*
|
|
* Host mode can be signalled via SW means or via SCRPD_DEBUGGER_IN_USE
|
|
* bit. Either way, don't reset HW in this case, and don't export any
|
|
* capture configuration attributes. Also, refuse to assign output
|
|
* drivers to ports, see intel_th_gth_assign().
|
|
*/
|
|
if (thdev->host_mode)
|
|
return 0;
|
|
|
|
ret = intel_th_gth_reset(gth);
|
|
if (ret) {
|
|
if (ret != -EBUSY)
|
|
return ret;
|
|
|
|
thdev->host_mode = true;
|
|
|
|
return 0;
|
|
}
|
|
|
|
for (i = 0; i < TH_CONFIGURABLE_MASTERS + 1; i++)
|
|
gth->master[i] = -1;
|
|
|
|
for (i = 0; i < TH_POSSIBLE_OUTPUTS; i++) {
|
|
gth->output[i].gth = gth;
|
|
gth->output[i].index = i;
|
|
gth->output[i].port_type =
|
|
gth_output_parm_get(gth, i, TH_OUTPUT_PARM(port));
|
|
if (gth->output[i].port_type == GTH_NONE)
|
|
continue;
|
|
|
|
ret = intel_th_output_enable(th, gth->output[i].port_type);
|
|
/* -ENODEV is ok, we just won't have that device enumerated */
|
|
if (ret && ret != -ENODEV)
|
|
return ret;
|
|
}
|
|
|
|
if (intel_th_output_attributes(gth) ||
|
|
intel_th_master_attributes(gth)) {
|
|
pr_warn("Can't initialize sysfs attributes\n");
|
|
|
|
if (gth->output_group.attrs)
|
|
sysfs_remove_group(>h->dev->kobj, >h->output_group);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void intel_th_gth_remove(struct intel_th_device *thdev)
|
|
{
|
|
struct gth_device *gth = dev_get_drvdata(&thdev->dev);
|
|
|
|
sysfs_remove_group(>h->dev->kobj, >h->output_group);
|
|
sysfs_remove_group(>h->dev->kobj, >h->master_group);
|
|
}
|
|
|
|
static struct intel_th_driver intel_th_gth_driver = {
|
|
.probe = intel_th_gth_probe,
|
|
.remove = intel_th_gth_remove,
|
|
.assign = intel_th_gth_assign,
|
|
.unassign = intel_th_gth_unassign,
|
|
.set_output = intel_th_gth_set_output,
|
|
.prepare = intel_th_gth_prepare,
|
|
.enable = intel_th_gth_enable,
|
|
.trig_switch = intel_th_gth_switch,
|
|
.disable = intel_th_gth_disable,
|
|
.driver = {
|
|
.name = "gth",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
module_driver(intel_th_gth_driver,
|
|
intel_th_driver_register,
|
|
intel_th_driver_unregister);
|
|
|
|
MODULE_ALIAS("intel_th_switch");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("Intel(R) Trace Hub Global Trace Hub driver");
|
|
MODULE_AUTHOR("Alexander Shishkin <alexander.shishkin@linux.intel.com>");
|