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![Thomas Gleixner](/assets/img/avatar_default.png)
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license gpl version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 66 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141901.606369721@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
182 lines
4.3 KiB
C
182 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
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* Copyright (c) 2014- QLogic Corporation.
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* All rights reserved
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* www.qlogic.com
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*
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* Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
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*/
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#include "bfad_drv.h"
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#include "bfa_modules.h"
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#include "bfi_reg.h"
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void
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bfa_hwcb_reginit(struct bfa_s *bfa)
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{
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struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
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void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
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int fn = bfa_ioc_pcifn(&bfa->ioc);
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if (fn == 0) {
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bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS);
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bfa_regs->intr_mask = (kva + HOSTFN0_INT_MSK);
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} else {
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bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS);
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bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK);
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}
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}
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static void
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bfa_hwcb_reqq_ack_msix(struct bfa_s *bfa, int reqq)
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{
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writel(__HFN_INT_CPE_Q0 << CPE_Q_NUM(bfa_ioc_pcifn(&bfa->ioc), reqq),
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bfa->iocfc.bfa_regs.intr_status);
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}
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/*
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* Actions to respond RME Interrupt for Crossbow ASIC:
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* - Write 1 to Interrupt Status register
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* INTX - done in bfa_intx()
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* MSIX - done in bfa_hwcb_rspq_ack_msix()
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* - Update CI (only if new CI)
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*/
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static void
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bfa_hwcb_rspq_ack_msix(struct bfa_s *bfa, int rspq, u32 ci)
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{
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writel(__HFN_INT_RME_Q0 << RME_Q_NUM(bfa_ioc_pcifn(&bfa->ioc), rspq),
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bfa->iocfc.bfa_regs.intr_status);
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if (bfa_rspq_ci(bfa, rspq) == ci)
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return;
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bfa_rspq_ci(bfa, rspq) = ci;
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writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]);
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}
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void
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bfa_hwcb_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci)
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{
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if (bfa_rspq_ci(bfa, rspq) == ci)
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return;
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bfa_rspq_ci(bfa, rspq) = ci;
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writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]);
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}
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void
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bfa_hwcb_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap,
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u32 *num_vecs, u32 *max_vec_bit)
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{
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#define __HFN_NUMINTS 13
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if (bfa_ioc_pcifn(&bfa->ioc) == 0) {
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*msix_vecs_bmap = (__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 |
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__HFN_INT_CPE_Q2 | __HFN_INT_CPE_Q3 |
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__HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 |
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__HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 |
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__HFN_INT_MBOX_LPU0);
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*max_vec_bit = __HFN_INT_MBOX_LPU0;
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} else {
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*msix_vecs_bmap = (__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 |
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__HFN_INT_CPE_Q6 | __HFN_INT_CPE_Q7 |
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__HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 |
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__HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 |
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__HFN_INT_MBOX_LPU1);
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*max_vec_bit = __HFN_INT_MBOX_LPU1;
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}
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*msix_vecs_bmap |= (__HFN_INT_ERR_EMC | __HFN_INT_ERR_LPU0 |
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__HFN_INT_ERR_LPU1 | __HFN_INT_ERR_PSS);
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*num_vecs = __HFN_NUMINTS;
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}
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/*
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* Dummy interrupt handler for handling spurious interrupts.
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*/
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static void
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bfa_hwcb_msix_dummy(struct bfa_s *bfa, int vec)
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{
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}
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/*
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* No special setup required for crossbow -- vector assignments are implicit.
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*/
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void
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bfa_hwcb_msix_init(struct bfa_s *bfa, int nvecs)
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{
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WARN_ON((nvecs != 1) && (nvecs != __HFN_NUMINTS));
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bfa->msix.nvecs = nvecs;
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bfa_hwcb_msix_uninstall(bfa);
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}
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void
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bfa_hwcb_msix_ctrl_install(struct bfa_s *bfa)
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{
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int i;
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if (bfa->msix.nvecs == 0)
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return;
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if (bfa->msix.nvecs == 1) {
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for (i = BFI_MSIX_CPE_QMIN_CB; i < BFI_MSIX_CB_MAX; i++)
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bfa->msix.handler[i] = bfa_msix_all;
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return;
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}
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for (i = BFI_MSIX_RME_QMAX_CB+1; i < BFI_MSIX_CB_MAX; i++)
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bfa->msix.handler[i] = bfa_msix_lpu_err;
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}
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void
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bfa_hwcb_msix_queue_install(struct bfa_s *bfa)
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{
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int i;
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if (bfa->msix.nvecs == 0)
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return;
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if (bfa->msix.nvecs == 1) {
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for (i = BFI_MSIX_CPE_QMIN_CB; i <= BFI_MSIX_RME_QMAX_CB; i++)
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bfa->msix.handler[i] = bfa_msix_all;
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return;
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}
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for (i = BFI_MSIX_CPE_QMIN_CB; i <= BFI_MSIX_CPE_QMAX_CB; i++)
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bfa->msix.handler[i] = bfa_msix_reqq;
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for (i = BFI_MSIX_RME_QMIN_CB; i <= BFI_MSIX_RME_QMAX_CB; i++)
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bfa->msix.handler[i] = bfa_msix_rspq;
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}
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void
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bfa_hwcb_msix_uninstall(struct bfa_s *bfa)
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{
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int i;
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for (i = 0; i < BFI_MSIX_CB_MAX; i++)
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bfa->msix.handler[i] = bfa_hwcb_msix_dummy;
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}
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/*
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* No special enable/disable -- vector assignments are implicit.
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*/
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void
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bfa_hwcb_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix)
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{
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if (msix) {
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bfa->iocfc.hwif.hw_reqq_ack = bfa_hwcb_reqq_ack_msix;
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bfa->iocfc.hwif.hw_rspq_ack = bfa_hwcb_rspq_ack_msix;
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} else {
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bfa->iocfc.hwif.hw_reqq_ack = NULL;
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bfa->iocfc.hwif.hw_rspq_ack = bfa_hwcb_rspq_ack;
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}
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}
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void
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bfa_hwcb_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end)
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{
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*start = BFI_MSIX_RME_QMIN_CB;
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*end = BFI_MSIX_RME_QMAX_CB;
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}
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