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![Jae Hyun Yoo](/assets/img/avatar_default.png)
Add a checking code when it gets -EPROBE_DEFER while getting a clock resource. In this case, it doesn't need to print out an error message because the probing will be re-visited. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Iwona Winiarska <iwona.winiarska@intel.com> Link: https://lore.kernel.org/r/20211104173709.222912-1-jae.hyun.yoo@intel.com Link: https://lore.kernel.org/r/20220201070118.196372-1-joel@jms.id.au' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
366 lines
9.4 KiB
C
366 lines
9.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2017 IBM Corporation
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*/
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#include <linux/clk.h>
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#include <linux/log2.h>
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#include <linux/mfd/syscon.h>
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#include <linux/miscdevice.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/poll.h>
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#include <linux/regmap.h>
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#include <linux/aspeed-lpc-ctrl.h>
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#define DEVICE_NAME "aspeed-lpc-ctrl"
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#define HICR5 0x80
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#define HICR5_ENL2H BIT(8)
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#define HICR5_ENFWH BIT(10)
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#define HICR6 0x84
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#define SW_FWH2AHB BIT(17)
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#define HICR7 0x88
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#define HICR8 0x8c
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struct aspeed_lpc_ctrl {
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struct miscdevice miscdev;
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struct regmap *regmap;
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struct clk *clk;
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phys_addr_t mem_base;
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resource_size_t mem_size;
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u32 pnor_size;
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u32 pnor_base;
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bool fwh2ahb;
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struct regmap *scu;
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};
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static struct aspeed_lpc_ctrl *file_aspeed_lpc_ctrl(struct file *file)
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{
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return container_of(file->private_data, struct aspeed_lpc_ctrl,
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miscdev);
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}
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static int aspeed_lpc_ctrl_mmap(struct file *file, struct vm_area_struct *vma)
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{
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struct aspeed_lpc_ctrl *lpc_ctrl = file_aspeed_lpc_ctrl(file);
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unsigned long vsize = vma->vm_end - vma->vm_start;
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pgprot_t prot = vma->vm_page_prot;
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if (vma->vm_pgoff + vma_pages(vma) > lpc_ctrl->mem_size >> PAGE_SHIFT)
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return -EINVAL;
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/* ast2400/2500 AHB accesses are not cache coherent */
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prot = pgprot_noncached(prot);
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if (remap_pfn_range(vma, vma->vm_start,
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(lpc_ctrl->mem_base >> PAGE_SHIFT) + vma->vm_pgoff,
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vsize, prot))
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return -EAGAIN;
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return 0;
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}
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static long aspeed_lpc_ctrl_ioctl(struct file *file, unsigned int cmd,
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unsigned long param)
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{
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struct aspeed_lpc_ctrl *lpc_ctrl = file_aspeed_lpc_ctrl(file);
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struct device *dev = file->private_data;
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void __user *p = (void __user *)param;
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struct aspeed_lpc_ctrl_mapping map;
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u32 addr;
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u32 size;
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long rc;
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if (copy_from_user(&map, p, sizeof(map)))
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return -EFAULT;
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if (map.flags != 0)
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return -EINVAL;
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switch (cmd) {
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case ASPEED_LPC_CTRL_IOCTL_GET_SIZE:
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/* The flash windows don't report their size */
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if (map.window_type != ASPEED_LPC_CTRL_WINDOW_MEMORY)
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return -EINVAL;
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/* Support more than one window id in the future */
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if (map.window_id != 0)
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return -EINVAL;
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/* If memory-region is not described in device tree */
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if (!lpc_ctrl->mem_size) {
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dev_dbg(dev, "Didn't find reserved memory\n");
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return -ENXIO;
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}
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map.size = lpc_ctrl->mem_size;
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return copy_to_user(p, &map, sizeof(map)) ? -EFAULT : 0;
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case ASPEED_LPC_CTRL_IOCTL_MAP:
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/*
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* The top half of HICR7 is the MSB of the BMC address of the
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* mapping.
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* The bottom half of HICR7 is the MSB of the HOST LPC
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* firmware space address of the mapping.
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*
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* The 1 bits in the top of half of HICR8 represent the bits
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* (in the requested address) that should be ignored and
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* replaced with those from the top half of HICR7.
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* The 1 bits in the bottom half of HICR8 represent the bits
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* (in the requested address) that should be kept and pass
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* into the BMC address space.
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*/
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/*
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* It doesn't make sense to talk about a size or offset with
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* low 16 bits set. Both HICR7 and HICR8 talk about the top 16
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* bits of addresses and sizes.
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*/
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if ((map.size & 0x0000ffff) || (map.offset & 0x0000ffff))
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return -EINVAL;
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/*
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* Because of the way the masks work in HICR8 offset has to
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* be a multiple of size.
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*/
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if (map.offset & (map.size - 1))
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return -EINVAL;
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if (map.window_type == ASPEED_LPC_CTRL_WINDOW_FLASH) {
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if (!lpc_ctrl->pnor_size) {
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dev_dbg(dev, "Didn't find host pnor flash\n");
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return -ENXIO;
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}
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addr = lpc_ctrl->pnor_base;
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size = lpc_ctrl->pnor_size;
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} else if (map.window_type == ASPEED_LPC_CTRL_WINDOW_MEMORY) {
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/* If memory-region is not described in device tree */
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if (!lpc_ctrl->mem_size) {
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dev_dbg(dev, "Didn't find reserved memory\n");
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return -ENXIO;
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}
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addr = lpc_ctrl->mem_base;
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size = lpc_ctrl->mem_size;
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} else {
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return -EINVAL;
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}
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/* Check overflow first! */
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if (map.offset + map.size < map.offset ||
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map.offset + map.size > size)
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return -EINVAL;
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if (map.size == 0 || map.size > size)
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return -EINVAL;
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addr += map.offset;
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/*
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* addr (host lpc address) is safe regardless of values. This
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* simply changes the address the host has to request on its
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* side of the LPC bus. This cannot impact the hosts own
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* memory space by surprise as LPC specific accessors are
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* required. The only strange thing that could be done is
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* setting the lower 16 bits but the shift takes care of that.
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*/
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rc = regmap_write(lpc_ctrl->regmap, HICR7,
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(addr | (map.addr >> 16)));
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if (rc)
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return rc;
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rc = regmap_write(lpc_ctrl->regmap, HICR8,
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(~(map.size - 1)) | ((map.size >> 16) - 1));
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if (rc)
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return rc;
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/*
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* Switch to FWH2AHB mode, AST2600 only.
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*/
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if (lpc_ctrl->fwh2ahb) {
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/*
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* Enable FWH2AHB in SCU debug control register 2. This
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* does not turn it on, but makes it available for it
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* to be configured in HICR6.
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*/
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regmap_update_bits(lpc_ctrl->scu, 0x0D8, BIT(2), 0);
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/*
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* The other bits in this register are interrupt status bits
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* that are cleared by writing 1. As we don't want to clear
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* them, set only the bit of interest.
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*/
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regmap_write(lpc_ctrl->regmap, HICR6, SW_FWH2AHB);
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}
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/*
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* Enable LPC FHW cycles. This is required for the host to
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* access the regions specified.
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*/
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return regmap_update_bits(lpc_ctrl->regmap, HICR5,
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HICR5_ENFWH | HICR5_ENL2H,
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HICR5_ENFWH | HICR5_ENL2H);
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}
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return -EINVAL;
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}
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static const struct file_operations aspeed_lpc_ctrl_fops = {
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.owner = THIS_MODULE,
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.mmap = aspeed_lpc_ctrl_mmap,
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.unlocked_ioctl = aspeed_lpc_ctrl_ioctl,
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};
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static int aspeed_lpc_ctrl_probe(struct platform_device *pdev)
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{
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struct aspeed_lpc_ctrl *lpc_ctrl;
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struct device_node *node;
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struct resource resm;
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struct device *dev;
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struct device_node *np;
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int rc;
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dev = &pdev->dev;
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lpc_ctrl = devm_kzalloc(dev, sizeof(*lpc_ctrl), GFP_KERNEL);
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if (!lpc_ctrl)
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return -ENOMEM;
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/* If flash is described in device tree then store */
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node = of_parse_phandle(dev->of_node, "flash", 0);
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if (!node) {
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dev_dbg(dev, "Didn't find host pnor flash node\n");
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} else {
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rc = of_address_to_resource(node, 1, &resm);
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of_node_put(node);
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if (rc) {
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dev_err(dev, "Couldn't address to resource for flash\n");
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return rc;
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}
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lpc_ctrl->pnor_size = resource_size(&resm);
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lpc_ctrl->pnor_base = resm.start;
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}
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dev_set_drvdata(&pdev->dev, lpc_ctrl);
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/* If memory-region is described in device tree then store */
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node = of_parse_phandle(dev->of_node, "memory-region", 0);
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if (!node) {
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dev_dbg(dev, "Didn't find reserved memory\n");
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} else {
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rc = of_address_to_resource(node, 0, &resm);
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of_node_put(node);
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if (rc) {
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dev_err(dev, "Couldn't address to resource for reserved memory\n");
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return -ENXIO;
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}
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lpc_ctrl->mem_size = resource_size(&resm);
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lpc_ctrl->mem_base = resm.start;
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if (!is_power_of_2(lpc_ctrl->mem_size)) {
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dev_err(dev, "Reserved memory size must be a power of 2, got %u\n",
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(unsigned int)lpc_ctrl->mem_size);
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return -EINVAL;
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}
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if (!IS_ALIGNED(lpc_ctrl->mem_base, lpc_ctrl->mem_size)) {
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dev_err(dev, "Reserved memory must be naturally aligned for size %u\n",
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(unsigned int)lpc_ctrl->mem_size);
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return -EINVAL;
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}
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}
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np = pdev->dev.parent->of_node;
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if (!of_device_is_compatible(np, "aspeed,ast2400-lpc-v2") &&
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!of_device_is_compatible(np, "aspeed,ast2500-lpc-v2") &&
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!of_device_is_compatible(np, "aspeed,ast2600-lpc-v2")) {
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dev_err(dev, "unsupported LPC device binding\n");
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return -ENODEV;
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}
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lpc_ctrl->regmap = syscon_node_to_regmap(np);
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if (IS_ERR(lpc_ctrl->regmap)) {
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dev_err(dev, "Couldn't get regmap\n");
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return -ENODEV;
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}
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if (of_device_is_compatible(dev->of_node, "aspeed,ast2600-lpc-ctrl")) {
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lpc_ctrl->fwh2ahb = true;
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lpc_ctrl->scu = syscon_regmap_lookup_by_compatible("aspeed,ast2600-scu");
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if (IS_ERR(lpc_ctrl->scu)) {
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dev_err(dev, "couldn't find scu\n");
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return PTR_ERR(lpc_ctrl->scu);
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}
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}
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lpc_ctrl->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(lpc_ctrl->clk))
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return dev_err_probe(dev, PTR_ERR(lpc_ctrl->clk),
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"couldn't get clock\n");
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rc = clk_prepare_enable(lpc_ctrl->clk);
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if (rc) {
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dev_err(dev, "couldn't enable clock\n");
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return rc;
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}
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lpc_ctrl->miscdev.minor = MISC_DYNAMIC_MINOR;
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lpc_ctrl->miscdev.name = DEVICE_NAME;
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lpc_ctrl->miscdev.fops = &aspeed_lpc_ctrl_fops;
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lpc_ctrl->miscdev.parent = dev;
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rc = misc_register(&lpc_ctrl->miscdev);
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if (rc) {
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dev_err(dev, "Unable to register device\n");
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goto err;
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}
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return 0;
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err:
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clk_disable_unprepare(lpc_ctrl->clk);
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return rc;
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}
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static int aspeed_lpc_ctrl_remove(struct platform_device *pdev)
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{
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struct aspeed_lpc_ctrl *lpc_ctrl = dev_get_drvdata(&pdev->dev);
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misc_deregister(&lpc_ctrl->miscdev);
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clk_disable_unprepare(lpc_ctrl->clk);
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return 0;
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}
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static const struct of_device_id aspeed_lpc_ctrl_match[] = {
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{ .compatible = "aspeed,ast2400-lpc-ctrl" },
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{ .compatible = "aspeed,ast2500-lpc-ctrl" },
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{ .compatible = "aspeed,ast2600-lpc-ctrl" },
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{ },
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};
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static struct platform_driver aspeed_lpc_ctrl_driver = {
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.driver = {
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.name = DEVICE_NAME,
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.of_match_table = aspeed_lpc_ctrl_match,
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},
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.probe = aspeed_lpc_ctrl_probe,
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.remove = aspeed_lpc_ctrl_remove,
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};
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module_platform_driver(aspeed_lpc_ctrl_driver);
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MODULE_DEVICE_TABLE(of, aspeed_lpc_ctrl_match);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Cyril Bur <cyrilbur@gmail.com>");
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MODULE_DESCRIPTION("Control for ASPEED LPC HOST to BMC mappings");
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