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fb6d1d3b25
When "bus_prot_reg_update" is true, the driver should use INFRA_TOPAXI_PROTECTEN for both setting and clearing the bus protection. However, the driver does not use this mask for clearing bus protection which causes failure when booting the imgtec gpu. Corrected and tested with mt8173 chromebook. Signed-off-by: Bilal Wasim <Bilal.Wasim@imgtec.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org> Link: https://lore.kernel.org/r/20210701114012.RESEND.1.I27436c29c3bede46dcf86df696f48683662d1ec1@changeid Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
106 lines
3 KiB
C
106 lines
3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MTK_PM_DOMAINS_H
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#define __SOC_MEDIATEK_MTK_PM_DOMAINS_H
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#define MTK_SCPD_ACTIVE_WAKEUP BIT(0)
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#define MTK_SCPD_FWAIT_SRAM BIT(1)
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#define MTK_SCPD_SRAM_ISO BIT(2)
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#define MTK_SCPD_KEEP_DEFAULT_OFF BIT(3)
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#define MTK_SCPD_DOMAIN_SUPPLY BIT(4)
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#define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
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#define SPM_VDE_PWR_CON 0x0210
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#define SPM_MFG_PWR_CON 0x0214
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#define SPM_VEN_PWR_CON 0x0230
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#define SPM_ISP_PWR_CON 0x0238
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#define SPM_DIS_PWR_CON 0x023c
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#define SPM_CONN_PWR_CON 0x0280
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#define SPM_VEN2_PWR_CON 0x0298
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#define SPM_AUDIO_PWR_CON 0x029c
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#define SPM_MFG_2D_PWR_CON 0x02c0
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#define SPM_MFG_ASYNC_PWR_CON 0x02c4
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#define SPM_USB_PWR_CON 0x02cc
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#define SPM_PWR_STATUS 0x060c
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#define SPM_PWR_STATUS_2ND 0x0610
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#define PWR_STATUS_CONN BIT(1)
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#define PWR_STATUS_DISP BIT(3)
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#define PWR_STATUS_MFG BIT(4)
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#define PWR_STATUS_ISP BIT(5)
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#define PWR_STATUS_VDEC BIT(7)
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#define PWR_STATUS_VENC_LT BIT(20)
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#define PWR_STATUS_VENC BIT(21)
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#define PWR_STATUS_MFG_2D BIT(22)
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#define PWR_STATUS_MFG_ASYNC BIT(23)
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#define PWR_STATUS_AUDIO BIT(24)
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#define PWR_STATUS_USB BIT(25)
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#define SPM_MAX_BUS_PROT_DATA 5
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#define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \
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.bus_prot_mask = (_mask), \
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.bus_prot_set = _set, \
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.bus_prot_clr = _clr, \
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.bus_prot_sta = _sta, \
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.bus_prot_reg_update = _update, \
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.ignore_clr_ack = _ignore, \
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}
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#define BUS_PROT_WR(_mask, _set, _clr, _sta) \
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_BUS_PROT(_mask, _set, _clr, _sta, false, false)
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#define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \
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_BUS_PROT(_mask, _set, _clr, _sta, false, true)
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#define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \
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_BUS_PROT(_mask, _set, _clr, _sta, true, false)
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#define BUS_PROT_UPDATE_TOPAXI(_mask) \
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BUS_PROT_UPDATE(_mask, \
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INFRA_TOPAXI_PROTECTEN, \
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INFRA_TOPAXI_PROTECTEN, \
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INFRA_TOPAXI_PROTECTSTA1)
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struct scpsys_bus_prot_data {
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u32 bus_prot_mask;
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u32 bus_prot_set;
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u32 bus_prot_clr;
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u32 bus_prot_sta;
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bool bus_prot_reg_update;
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bool ignore_clr_ack;
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};
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#define MAX_SUBSYS_CLKS 10
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/**
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* struct scpsys_domain_data - scp domain data for power on/off flow
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* @name: The name of the power domain.
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* @sta_mask: The mask for power on/off status bit.
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* @ctl_offs: The offset for main power control register.
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* @sram_pdn_bits: The mask for sram power control bits.
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* @sram_pdn_ack_bits: The mask for sram power control acked bits.
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* @caps: The flag for active wake-up action.
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* @bp_infracfg: bus protection for infracfg subsystem
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* @bp_smi: bus protection for smi subsystem
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*/
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struct scpsys_domain_data {
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const char *name;
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u32 sta_mask;
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int ctl_offs;
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u32 sram_pdn_bits;
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u32 sram_pdn_ack_bits;
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u8 caps;
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const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA];
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const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA];
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};
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struct scpsys_soc_data {
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const struct scpsys_domain_data *domains_data;
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int num_domains;
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int pwr_sta_offs;
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int pwr_sta2nd_offs;
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};
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#endif /* __SOC_MEDIATEK_MTK_PM_DOMAINS_H */
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