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![Haojian Zhuang](/assets/img/avatar_default.png)
In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b01 should be set as setting divider, it also needs to indicate the change by setting hiword mask (b11 << 16). The patch adds divider flag for this usage. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
343 lines
9 KiB
C
343 lines
9 KiB
C
/*
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* Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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* Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
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* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Adjustable divider clock implementation
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/string.h>
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#include <linux/log2.h>
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/*
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* DOC: basic adjustable divider clock that cannot gate
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*
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* Traits of this clock:
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* prepare - clk_prepare only ensures that parents are prepared
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* enable - clk_enable only ensures that parents are enabled
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* rate - rate is adjustable. clk->rate = parent->rate / divisor
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* parent - fixed parent. No clk_set_parent support
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*/
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#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
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#define div_mask(d) ((1 << ((d)->width)) - 1)
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static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
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{
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unsigned int maxdiv = 0;
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->div > maxdiv)
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maxdiv = clkt->div;
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return maxdiv;
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}
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static unsigned int _get_maxdiv(struct clk_divider *divider)
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{
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if (divider->flags & CLK_DIVIDER_ONE_BASED)
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return div_mask(divider);
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if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
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return 1 << div_mask(divider);
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if (divider->table)
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return _get_table_maxdiv(divider->table);
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return div_mask(divider) + 1;
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}
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static unsigned int _get_table_div(const struct clk_div_table *table,
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unsigned int val)
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{
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->val == val)
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return clkt->div;
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return 0;
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}
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static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
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{
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if (divider->flags & CLK_DIVIDER_ONE_BASED)
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return val;
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if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
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return 1 << val;
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if (divider->table)
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return _get_table_div(divider->table, val);
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return val + 1;
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}
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static unsigned int _get_table_val(const struct clk_div_table *table,
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unsigned int div)
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{
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->div == div)
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return clkt->val;
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return 0;
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}
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static unsigned int _get_val(struct clk_divider *divider, u8 div)
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{
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if (divider->flags & CLK_DIVIDER_ONE_BASED)
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return div;
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if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
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return __ffs(div);
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if (divider->table)
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return _get_table_val(divider->table, div);
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return div - 1;
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}
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static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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unsigned int div, val;
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val = readl(divider->reg) >> divider->shift;
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val &= div_mask(divider);
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div = _get_div(divider, val);
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if (!div) {
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WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
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"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
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__clk_get_name(hw->clk));
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return parent_rate;
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}
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return parent_rate / div;
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}
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/*
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* The reverse of DIV_ROUND_UP: The maximum number which
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* divided by m is r
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*/
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#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
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static bool _is_valid_table_div(const struct clk_div_table *table,
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unsigned int div)
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{
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->div == div)
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return true;
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return false;
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}
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static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
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{
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if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
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return is_power_of_2(div);
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if (divider->table)
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return _is_valid_table_div(divider->table, div);
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return true;
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}
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static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
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unsigned long *best_parent_rate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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int i, bestdiv = 0;
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unsigned long parent_rate, best = 0, now, maxdiv;
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unsigned long parent_rate_saved = *best_parent_rate;
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if (!rate)
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rate = 1;
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maxdiv = _get_maxdiv(divider);
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if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
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parent_rate = *best_parent_rate;
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bestdiv = DIV_ROUND_UP(parent_rate, rate);
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bestdiv = bestdiv == 0 ? 1 : bestdiv;
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bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
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return bestdiv;
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}
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/*
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* The maximum divider we can use without overflowing
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* unsigned long in rate * i below
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*/
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maxdiv = min(ULONG_MAX / rate, maxdiv);
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for (i = 1; i <= maxdiv; i++) {
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if (!_is_valid_div(divider, i))
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continue;
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if (rate * i == parent_rate_saved) {
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/*
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* It's the most ideal case if the requested rate can be
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* divided from parent clock without needing to change
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* parent rate, so return the divider immediately.
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*/
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*best_parent_rate = parent_rate_saved;
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return i;
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}
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parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
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MULT_ROUND_UP(rate, i));
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now = parent_rate / i;
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if (now <= rate && now > best) {
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bestdiv = i;
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best = now;
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*best_parent_rate = parent_rate;
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}
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}
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if (!bestdiv) {
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bestdiv = _get_maxdiv(divider);
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*best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
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}
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return bestdiv;
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}
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static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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int div;
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div = clk_divider_bestdiv(hw, rate, prate);
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return *prate / div;
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}
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static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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unsigned int div, value;
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unsigned long flags = 0;
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u32 val;
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div = parent_rate / rate;
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value = _get_val(divider, div);
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if (value > div_mask(divider))
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value = div_mask(divider);
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if (divider->lock)
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spin_lock_irqsave(divider->lock, flags);
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if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
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val = div_mask(divider) << (divider->shift + 16);
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} else {
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val = readl(divider->reg);
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val &= ~(div_mask(divider) << divider->shift);
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}
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val |= value << divider->shift;
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writel(val, divider->reg);
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if (divider->lock)
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spin_unlock_irqrestore(divider->lock, flags);
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return 0;
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}
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const struct clk_ops clk_divider_ops = {
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.recalc_rate = clk_divider_recalc_rate,
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.round_rate = clk_divider_round_rate,
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.set_rate = clk_divider_set_rate,
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};
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EXPORT_SYMBOL_GPL(clk_divider_ops);
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static struct clk *_register_divider(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags, const struct clk_div_table *table,
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spinlock_t *lock)
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{
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struct clk_divider *div;
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struct clk *clk;
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struct clk_init_data init;
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if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
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if (width + shift > 16) {
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pr_warn("divider value exceeds LOWORD field\n");
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return ERR_PTR(-EINVAL);
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}
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}
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/* allocate the divider */
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div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
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if (!div) {
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pr_err("%s: could not allocate divider clk\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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init.name = name;
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init.ops = &clk_divider_ops;
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init.flags = flags | CLK_IS_BASIC;
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init.parent_names = (parent_name ? &parent_name: NULL);
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init.num_parents = (parent_name ? 1 : 0);
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/* struct clk_divider assignments */
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div->reg = reg;
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div->shift = shift;
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div->width = width;
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div->flags = clk_divider_flags;
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div->lock = lock;
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div->hw.init = &init;
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div->table = table;
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/* register the clock */
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clk = clk_register(dev, &div->hw);
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if (IS_ERR(clk))
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kfree(div);
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return clk;
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}
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/**
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* clk_register_divider - register a divider clock with the clock framework
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* @dev: device registering this clock
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* @name: name of this clock
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* @parent_name: name of clock's parent
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* @flags: framework-specific flags
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* @reg: register address to adjust divider
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* @shift: number of bits to shift the bitfield
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* @width: width of the bitfield
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* @clk_divider_flags: divider-specific flags for this clock
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* @lock: shared register lock for this clock
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*/
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struct clk *clk_register_divider(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags, spinlock_t *lock)
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{
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return _register_divider(dev, name, parent_name, flags, reg, shift,
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width, clk_divider_flags, NULL, lock);
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}
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/**
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* clk_register_divider_table - register a table based divider clock with
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* the clock framework
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* @dev: device registering this clock
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* @name: name of this clock
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* @parent_name: name of clock's parent
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* @flags: framework-specific flags
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* @reg: register address to adjust divider
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* @shift: number of bits to shift the bitfield
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* @width: width of the bitfield
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* @clk_divider_flags: divider-specific flags for this clock
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* @table: array of divider/value pairs ending with a div set to 0
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* @lock: shared register lock for this clock
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*/
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struct clk *clk_register_divider_table(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags, const struct clk_div_table *table,
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spinlock_t *lock)
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{
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return _register_divider(dev, name, parent_name, flags, reg, shift,
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width, clk_divider_flags, table, lock);
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}
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