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![Heiko Stübner](/assets/img/avatar_default.png)
As the binding for slew-rate is under discussion and seems to need more tought it will get removed for now, so it doesn't get an offical release. Therefore remove it again from the only current user, tz1090. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
1024 lines
26 KiB
C
1024 lines
26 KiB
C
/*
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* Pinctrl driver for the Toumaz Xenif TZ1090 PowerDown Controller pins
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*
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* Copyright (c) 2013, Imagination Technologies Ltd.
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*
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* Derived from Tegra code:
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* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
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*
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* Derived from code:
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* Copyright (C) 2010 Google, Inc.
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* Copyright (C) 2010 NVIDIA Corporation
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* Copyright (C) 2009-2011 ST-Ericsson AB
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/slab.h>
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/*
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* The registers may be shared with other threads/cores, so we need to use the
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* metag global lock2 for atomicity.
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*/
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#include <asm/global_lock.h>
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#include "core.h"
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#include "pinconf.h"
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/* Register offsets from bank base address */
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#define REG_GPIO_CONTROL0 0x00
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#define REG_GPIO_CONTROL2 0x08
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/* Register field information */
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#define REG_GPIO_CONTROL2_PU_PD_S 16
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#define REG_GPIO_CONTROL2_PDC_POS_S 4
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#define REG_GPIO_CONTROL2_PDC_DR_S 2
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#define REG_GPIO_CONTROL2_PDC_SR_S 1
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#define REG_GPIO_CONTROL2_PDC_SCHMITT_S 0
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/* PU_PD field values */
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#define REG_PU_PD_TRISTATE 0
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#define REG_PU_PD_UP 1
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#define REG_PU_PD_DOWN 2
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#define REG_PU_PD_REPEATER 3
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/* DR field values */
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#define REG_DR_2mA 0
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#define REG_DR_4mA 1
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#define REG_DR_8mA 2
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#define REG_DR_12mA 3
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/**
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* struct tz1090_pdc_function - TZ1090 PDC pinctrl mux function
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* @name: The name of the function, exported to pinctrl core.
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* @groups: An array of pin groups that may select this function.
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* @ngroups: The number of entries in @groups.
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*/
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struct tz1090_pdc_function {
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const char *name;
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const char * const *groups;
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unsigned int ngroups;
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};
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/**
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* struct tz1090_pdc_pingroup - TZ1090 PDC pin group
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* @name: Name of pin group.
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* @pins: Array of pin numbers in this pin group.
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* @npins: Number of pins in this pin group.
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* @func: Function enabled by the mux.
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* @reg: Mux register offset.
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* @bit: Mux register bit.
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* @drv: Drive control supported, otherwise it's a mux.
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* This means Schmitt, Slew, and Drive strength.
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*
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* A representation of a group of pins (possibly just one pin) in the TZ1090
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* PDC pin controller. Each group allows some parameter or parameters to be
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* configured. The most common is mux function selection.
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*/
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struct tz1090_pdc_pingroup {
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const char *name;
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const unsigned int *pins;
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unsigned int npins;
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int func;
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u16 reg;
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u8 bit;
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bool drv;
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};
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/*
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* All PDC pins can be GPIOs. Define these first to match how the GPIO driver
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* names/numbers its pins.
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*/
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enum tz1090_pdc_pin {
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TZ1090_PDC_PIN_GPIO0,
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TZ1090_PDC_PIN_GPIO1,
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TZ1090_PDC_PIN_SYS_WAKE0,
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TZ1090_PDC_PIN_SYS_WAKE1,
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TZ1090_PDC_PIN_SYS_WAKE2,
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TZ1090_PDC_PIN_IR_DATA,
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TZ1090_PDC_PIN_EXT_POWER,
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};
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/* Pin names */
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static const struct pinctrl_pin_desc tz1090_pdc_pins[] = {
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/* PDC GPIOs */
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PINCTRL_PIN(TZ1090_PDC_PIN_GPIO0, "gpio0"),
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PINCTRL_PIN(TZ1090_PDC_PIN_GPIO1, "gpio1"),
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PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE0, "sys_wake0"),
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PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE1, "sys_wake1"),
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PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE2, "sys_wake2"),
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PINCTRL_PIN(TZ1090_PDC_PIN_IR_DATA, "ir_data"),
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PINCTRL_PIN(TZ1090_PDC_PIN_EXT_POWER, "ext_power"),
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};
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/* Pin group pins */
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static const unsigned int gpio0_pins[] = {
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TZ1090_PDC_PIN_GPIO0,
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};
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static const unsigned int gpio1_pins[] = {
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TZ1090_PDC_PIN_GPIO1,
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};
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static const unsigned int pdc_pins[] = {
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TZ1090_PDC_PIN_GPIO0,
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TZ1090_PDC_PIN_GPIO1,
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TZ1090_PDC_PIN_SYS_WAKE0,
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TZ1090_PDC_PIN_SYS_WAKE1,
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TZ1090_PDC_PIN_SYS_WAKE2,
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TZ1090_PDC_PIN_IR_DATA,
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TZ1090_PDC_PIN_EXT_POWER,
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};
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/* Mux functions */
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enum tz1090_pdc_mux {
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/* PDC_GPIO0 mux */
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TZ1090_PDC_MUX_IR_MOD_STABLE_OUT,
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/* PDC_GPIO1 mux */
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TZ1090_PDC_MUX_IR_MOD_POWER_OUT,
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};
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/* Pin groups a function can be muxed to */
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static const char * const gpio0_groups[] = {
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"gpio0",
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};
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static const char * const gpio1_groups[] = {
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"gpio1",
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};
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#define FUNCTION(mux, fname, group) \
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[(TZ1090_PDC_MUX_ ## mux)] = { \
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.name = #fname, \
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.groups = group##_groups, \
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.ngroups = ARRAY_SIZE(group##_groups), \
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}
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/* Must correlate with enum tz1090_pdc_mux */
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static const struct tz1090_pdc_function tz1090_pdc_functions[] = {
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/* MUX fn pingroups */
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FUNCTION(IR_MOD_STABLE_OUT, ir_mod_stable_out, gpio0),
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FUNCTION(IR_MOD_POWER_OUT, ir_mod_power_out, gpio1),
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};
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/**
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* MUX_PG() - Initialise a pin group with mux control
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* @pg_name: Pin group name (stringified, _pins appended to get pins array)
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* @f0: Function 0 (TZ1090_PDC_MUX_ is prepended)
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* @mux_r: Mux register (REG_PINCTRL_ is prepended)
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* @mux_b: Bit number in register of mux field
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*/
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#define MUX_PG(pg_name, f0, mux_r, mux_b) \
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{ \
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.name = #pg_name, \
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.pins = pg_name##_pins, \
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.npins = ARRAY_SIZE(pg_name##_pins), \
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.func = TZ1090_PDC_MUX_ ## f0, \
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.reg = (REG_ ## mux_r), \
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.bit = (mux_b), \
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}
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/**
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* DRV_PG() - Initialise a pin group with drive control
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* @pg_name: Pin group name (stringified, _pins appended to get pins array)
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*/
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#define DRV_PG(pg_name) \
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{ \
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.name = #pg_name, \
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.pins = pg_name##_pins, \
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.npins = ARRAY_SIZE(pg_name##_pins), \
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.drv = true, \
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}
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static const struct tz1090_pdc_pingroup tz1090_pdc_groups[] = {
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/* Muxing pin groups */
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/* pg_name, f0, mux register, mux bit */
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MUX_PG(gpio0, IR_MOD_STABLE_OUT, GPIO_CONTROL0, 7),
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MUX_PG(gpio1, IR_MOD_POWER_OUT, GPIO_CONTROL0, 6),
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/* Drive pin groups */
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/* pg_name */
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DRV_PG(pdc),
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};
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/**
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* struct tz1090_pdc_pmx - Private pinctrl data
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* @dev: Platform device
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* @pctl: Pin control device
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* @regs: Register region
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* @lock: Lock protecting coherency of mux_en and gpio_en
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* @mux_en: Muxes that have been enabled
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* @gpio_en: Muxable GPIOs that have been enabled
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*/
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struct tz1090_pdc_pmx {
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struct device *dev;
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struct pinctrl_dev *pctl;
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void __iomem *regs;
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spinlock_t lock;
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u32 mux_en;
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u32 gpio_en;
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};
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static inline u32 pmx_read(struct tz1090_pdc_pmx *pmx, u32 reg)
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{
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return ioread32(pmx->regs + reg);
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}
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static inline void pmx_write(struct tz1090_pdc_pmx *pmx, u32 val, u32 reg)
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{
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iowrite32(val, pmx->regs + reg);
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}
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/*
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* Pin control operations
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*/
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static int tz1090_pdc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
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{
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return ARRAY_SIZE(tz1090_pdc_groups);
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}
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static const char *tz1090_pdc_pinctrl_get_group_name(struct pinctrl_dev *pctl,
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unsigned int group)
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{
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return tz1090_pdc_groups[group].name;
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}
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static int tz1090_pdc_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
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unsigned int group,
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const unsigned int **pins,
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unsigned int *num_pins)
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{
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*pins = tz1090_pdc_groups[group].pins;
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*num_pins = tz1090_pdc_groups[group].npins;
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return 0;
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}
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#ifdef CONFIG_DEBUG_FS
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static void tz1090_pdc_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
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struct seq_file *s,
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unsigned int offset)
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{
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seq_printf(s, " %s", dev_name(pctldev->dev));
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}
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#endif
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static int reserve_map(struct device *dev, struct pinctrl_map **map,
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unsigned int *reserved_maps, unsigned int *num_maps,
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unsigned int reserve)
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{
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unsigned int old_num = *reserved_maps;
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unsigned int new_num = *num_maps + reserve;
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struct pinctrl_map *new_map;
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if (old_num >= new_num)
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return 0;
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new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
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if (!new_map) {
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dev_err(dev, "krealloc(map) failed\n");
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return -ENOMEM;
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}
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memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
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*map = new_map;
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*reserved_maps = new_num;
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return 0;
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}
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static int add_map_mux(struct pinctrl_map **map, unsigned int *reserved_maps,
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unsigned int *num_maps, const char *group,
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const char *function)
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{
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if (WARN_ON(*num_maps == *reserved_maps))
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return -ENOSPC;
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(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
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(*map)[*num_maps].data.mux.group = group;
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(*map)[*num_maps].data.mux.function = function;
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(*num_maps)++;
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return 0;
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}
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/**
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* get_group_selector() - returns the group selector for a group
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* @pin_group: the pin group to look up
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*
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* This is the same as pinctrl_get_group_selector except it doesn't produce an
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* error message if the group isn't found or debug messages.
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*/
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static int get_group_selector(const char *pin_group)
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{
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unsigned int group;
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for (group = 0; group < ARRAY_SIZE(tz1090_pdc_groups); ++group)
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if (!strcmp(tz1090_pdc_groups[group].name, pin_group))
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return group;
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return -EINVAL;
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}
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static int add_map_configs(struct device *dev,
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struct pinctrl_map **map,
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unsigned int *reserved_maps, unsigned int *num_maps,
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const char *group, unsigned long *configs,
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unsigned int num_configs)
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{
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unsigned long *dup_configs;
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enum pinctrl_map_type type;
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if (WARN_ON(*num_maps == *reserved_maps))
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return -ENOSPC;
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dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
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GFP_KERNEL);
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if (!dup_configs) {
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dev_err(dev, "kmemdup(configs) failed\n");
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return -ENOMEM;
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}
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/*
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* We support both pins and pin groups, but we need to figure out which
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* one we have.
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*/
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if (get_group_selector(group) >= 0)
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type = PIN_MAP_TYPE_CONFIGS_GROUP;
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else
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type = PIN_MAP_TYPE_CONFIGS_PIN;
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(*map)[*num_maps].type = type;
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(*map)[*num_maps].data.configs.group_or_pin = group;
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(*map)[*num_maps].data.configs.configs = dup_configs;
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(*map)[*num_maps].data.configs.num_configs = num_configs;
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(*num_maps)++;
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return 0;
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}
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static void tz1090_pdc_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
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struct pinctrl_map *map,
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unsigned int num_maps)
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{
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int i;
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for (i = 0; i < num_maps; i++)
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if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
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kfree(map[i].data.configs.configs);
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kfree(map);
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}
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static int tz1090_pdc_pinctrl_dt_subnode_to_map(struct device *dev,
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struct device_node *np,
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struct pinctrl_map **map,
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unsigned int *reserved_maps,
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unsigned int *num_maps)
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{
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int ret;
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const char *function;
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unsigned long *configs = NULL;
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unsigned int num_configs = 0;
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unsigned int reserve;
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struct property *prop;
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const char *group;
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ret = of_property_read_string(np, "tz1090,function", &function);
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if (ret < 0) {
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/* EINVAL=missing, which is fine since it's optional */
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if (ret != -EINVAL)
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dev_err(dev,
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"could not parse property function\n");
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function = NULL;
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}
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ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs);
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if (ret)
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return ret;
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reserve = 0;
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if (function != NULL)
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reserve++;
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if (num_configs)
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reserve++;
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ret = of_property_count_strings(np, "tz1090,pins");
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if (ret < 0) {
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dev_err(dev, "could not parse property pins\n");
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goto exit;
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}
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reserve *= ret;
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ret = reserve_map(dev, map, reserved_maps, num_maps, reserve);
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if (ret < 0)
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goto exit;
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of_property_for_each_string(np, "tz1090,pins", prop, group) {
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if (function) {
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ret = add_map_mux(map, reserved_maps, num_maps,
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group, function);
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if (ret < 0)
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goto exit;
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}
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if (num_configs) {
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ret = add_map_configs(dev, map, reserved_maps,
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num_maps, group, configs,
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num_configs);
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if (ret < 0)
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goto exit;
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}
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}
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ret = 0;
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exit:
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kfree(configs);
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return ret;
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}
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static int tz1090_pdc_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
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struct device_node *np_config,
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struct pinctrl_map **map,
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unsigned int *num_maps)
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{
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unsigned int reserved_maps;
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struct device_node *np;
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int ret;
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reserved_maps = 0;
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*map = NULL;
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*num_maps = 0;
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for_each_child_of_node(np_config, np) {
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ret = tz1090_pdc_pinctrl_dt_subnode_to_map(pctldev->dev, np,
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map, &reserved_maps,
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num_maps);
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if (ret < 0) {
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tz1090_pdc_pinctrl_dt_free_map(pctldev, *map,
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*num_maps);
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return ret;
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}
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}
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return 0;
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}
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static struct pinctrl_ops tz1090_pdc_pinctrl_ops = {
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.get_groups_count = tz1090_pdc_pinctrl_get_groups_count,
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.get_group_name = tz1090_pdc_pinctrl_get_group_name,
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.get_group_pins = tz1090_pdc_pinctrl_get_group_pins,
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#ifdef CONFIG_DEBUG_FS
|
|
.pin_dbg_show = tz1090_pdc_pinctrl_pin_dbg_show,
|
|
#endif
|
|
.dt_node_to_map = tz1090_pdc_pinctrl_dt_node_to_map,
|
|
.dt_free_map = tz1090_pdc_pinctrl_dt_free_map,
|
|
};
|
|
|
|
/*
|
|
* Pin mux operations
|
|
*/
|
|
|
|
static int tz1090_pdc_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
|
|
{
|
|
return ARRAY_SIZE(tz1090_pdc_functions);
|
|
}
|
|
|
|
static const char *tz1090_pdc_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
|
|
unsigned int function)
|
|
{
|
|
return tz1090_pdc_functions[function].name;
|
|
}
|
|
|
|
static int tz1090_pdc_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
|
|
unsigned int function,
|
|
const char * const **groups,
|
|
unsigned int * const num_groups)
|
|
{
|
|
*groups = tz1090_pdc_functions[function].groups;
|
|
*num_groups = tz1090_pdc_functions[function].ngroups;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* tz1090_pdc_pinctrl_mux() - update mux bit
|
|
* @pmx: Pinmux data
|
|
* @grp: Pin mux group
|
|
*/
|
|
static void tz1090_pdc_pinctrl_mux(struct tz1090_pdc_pmx *pmx,
|
|
const struct tz1090_pdc_pingroup *grp)
|
|
{
|
|
u32 reg, select;
|
|
unsigned int pin_shift = grp->pins[0];
|
|
unsigned long flags;
|
|
|
|
/* select = mux && !gpio */
|
|
select = ((pmx->mux_en & ~pmx->gpio_en) >> pin_shift) & 1;
|
|
|
|
/* set up the mux */
|
|
__global_lock2(flags);
|
|
reg = pmx_read(pmx, grp->reg);
|
|
reg &= ~BIT(grp->bit);
|
|
reg |= select << grp->bit;
|
|
pmx_write(pmx, reg, grp->reg);
|
|
__global_unlock2(flags);
|
|
}
|
|
|
|
static int tz1090_pdc_pinctrl_enable(struct pinctrl_dev *pctldev,
|
|
unsigned int function, unsigned int group)
|
|
{
|
|
struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
|
const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group];
|
|
|
|
dev_dbg(pctldev->dev, "%s(func=%u (%s), group=%u (%s))\n",
|
|
__func__,
|
|
function, tz1090_pdc_functions[function].name,
|
|
group, tz1090_pdc_groups[group].name);
|
|
|
|
/* is it even a mux? */
|
|
if (grp->drv)
|
|
return -EINVAL;
|
|
|
|
/* does this group even control the function? */
|
|
if (function != grp->func)
|
|
return -EINVAL;
|
|
|
|
/* record the pin being muxed and update mux bit */
|
|
spin_lock(&pmx->lock);
|
|
pmx->mux_en |= BIT(grp->pins[0]);
|
|
tz1090_pdc_pinctrl_mux(pmx, grp);
|
|
spin_unlock(&pmx->lock);
|
|
return 0;
|
|
}
|
|
|
|
static void tz1090_pdc_pinctrl_disable(struct pinctrl_dev *pctldev,
|
|
unsigned int function,
|
|
unsigned int group)
|
|
{
|
|
struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
|
const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group];
|
|
|
|
dev_dbg(pctldev->dev, "%s(func=%u (%s), group=%u (%s))\n",
|
|
__func__,
|
|
function, tz1090_pdc_functions[function].name,
|
|
group, tz1090_pdc_groups[group].name);
|
|
|
|
/* is it even a mux? */
|
|
if (grp->drv)
|
|
return;
|
|
|
|
/* does this group even control the function? */
|
|
if (function != grp->func)
|
|
return;
|
|
|
|
/* record the pin being unmuxed and update mux bit */
|
|
spin_lock(&pmx->lock);
|
|
pmx->mux_en &= ~BIT(grp->pins[0]);
|
|
tz1090_pdc_pinctrl_mux(pmx, grp);
|
|
spin_unlock(&pmx->lock);
|
|
}
|
|
|
|
static const struct tz1090_pdc_pingroup *find_mux_group(
|
|
struct tz1090_pdc_pmx *pmx,
|
|
unsigned int pin)
|
|
{
|
|
const struct tz1090_pdc_pingroup *grp;
|
|
unsigned int group;
|
|
|
|
grp = tz1090_pdc_groups;
|
|
for (group = 0; group < ARRAY_SIZE(tz1090_pdc_groups); ++group, ++grp) {
|
|
/* only match muxes */
|
|
if (grp->drv)
|
|
continue;
|
|
|
|
/* with a matching pin */
|
|
if (grp->pins[0] == pin)
|
|
return grp;
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static int tz1090_pdc_pinctrl_gpio_request_enable(
|
|
struct pinctrl_dev *pctldev,
|
|
struct pinctrl_gpio_range *range,
|
|
unsigned int pin)
|
|
{
|
|
struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
|
const struct tz1090_pdc_pingroup *grp = find_mux_group(pmx, pin);
|
|
|
|
if (grp) {
|
|
/* record the pin in GPIO use and update mux bit */
|
|
spin_lock(&pmx->lock);
|
|
pmx->gpio_en |= BIT(pin);
|
|
tz1090_pdc_pinctrl_mux(pmx, grp);
|
|
spin_unlock(&pmx->lock);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void tz1090_pdc_pinctrl_gpio_disable_free(
|
|
struct pinctrl_dev *pctldev,
|
|
struct pinctrl_gpio_range *range,
|
|
unsigned int pin)
|
|
{
|
|
struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
|
const struct tz1090_pdc_pingroup *grp = find_mux_group(pmx, pin);
|
|
|
|
if (grp) {
|
|
/* record the pin not in GPIO use and update mux bit */
|
|
spin_lock(&pmx->lock);
|
|
pmx->gpio_en &= ~BIT(pin);
|
|
tz1090_pdc_pinctrl_mux(pmx, grp);
|
|
spin_unlock(&pmx->lock);
|
|
}
|
|
}
|
|
|
|
static struct pinmux_ops tz1090_pdc_pinmux_ops = {
|
|
.get_functions_count = tz1090_pdc_pinctrl_get_funcs_count,
|
|
.get_function_name = tz1090_pdc_pinctrl_get_func_name,
|
|
.get_function_groups = tz1090_pdc_pinctrl_get_func_groups,
|
|
.enable = tz1090_pdc_pinctrl_enable,
|
|
.disable = tz1090_pdc_pinctrl_disable,
|
|
.gpio_request_enable = tz1090_pdc_pinctrl_gpio_request_enable,
|
|
.gpio_disable_free = tz1090_pdc_pinctrl_gpio_disable_free,
|
|
};
|
|
|
|
/*
|
|
* Pin config operations
|
|
*/
|
|
|
|
static int tz1090_pdc_pinconf_reg(struct pinctrl_dev *pctldev,
|
|
unsigned int pin,
|
|
enum pin_config_param param,
|
|
bool report_err,
|
|
u32 *reg, u32 *width, u32 *mask, u32 *shift,
|
|
u32 *val)
|
|
{
|
|
/* Find information about parameter's register */
|
|
switch (param) {
|
|
case PIN_CONFIG_BIAS_DISABLE:
|
|
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
|
|
*val = REG_PU_PD_TRISTATE;
|
|
break;
|
|
case PIN_CONFIG_BIAS_PULL_UP:
|
|
*val = REG_PU_PD_UP;
|
|
break;
|
|
case PIN_CONFIG_BIAS_PULL_DOWN:
|
|
*val = REG_PU_PD_DOWN;
|
|
break;
|
|
case PIN_CONFIG_BIAS_BUS_HOLD:
|
|
*val = REG_PU_PD_REPEATER;
|
|
break;
|
|
default:
|
|
return -ENOTSUPP;
|
|
};
|
|
|
|
/* Only input bias parameters supported */
|
|
*reg = REG_GPIO_CONTROL2;
|
|
*shift = REG_GPIO_CONTROL2_PU_PD_S + pin*2;
|
|
*width = 2;
|
|
|
|
/* Calculate field information */
|
|
*mask = (BIT(*width) - 1) << *shift;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tz1090_pdc_pinconf_get(struct pinctrl_dev *pctldev,
|
|
unsigned int pin, unsigned long *config)
|
|
{
|
|
struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
|
enum pin_config_param param = pinconf_to_config_param(*config);
|
|
int ret;
|
|
u32 reg, width, mask, shift, val, tmp, arg;
|
|
|
|
/* Get register information */
|
|
ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true,
|
|
®, &width, &mask, &shift, &val);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* Extract field from register */
|
|
tmp = pmx_read(pmx, reg);
|
|
arg = ((tmp & mask) >> shift) == val;
|
|
|
|
/* Config not active */
|
|
if (!arg)
|
|
return -EINVAL;
|
|
|
|
/* And pack config */
|
|
*config = pinconf_to_config_packed(param, arg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tz1090_pdc_pinconf_set(struct pinctrl_dev *pctldev,
|
|
unsigned int pin, unsigned long config)
|
|
{
|
|
struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
|
enum pin_config_param param = pinconf_to_config_param(config);
|
|
unsigned int arg = pinconf_to_config_argument(config);
|
|
int ret;
|
|
u32 reg, width, mask, shift, val, tmp;
|
|
unsigned long flags;
|
|
|
|
dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n",
|
|
__func__, tz1090_pdc_pins[pin].name, config);
|
|
|
|
/* Get register information */
|
|
ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true,
|
|
®, &width, &mask, &shift, &val);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* Unpack argument and range check it */
|
|
if (arg > 1) {
|
|
dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
|
|
__func__, arg);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Write register field */
|
|
__global_lock2(flags);
|
|
tmp = pmx_read(pmx, reg);
|
|
tmp &= ~mask;
|
|
if (arg)
|
|
tmp |= val << shift;
|
|
pmx_write(pmx, tmp, reg);
|
|
__global_unlock2(flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const int tz1090_pdc_boolean_map[] = {
|
|
[0] = -EINVAL,
|
|
[1] = 1,
|
|
};
|
|
|
|
static const int tz1090_pdc_dr_map[] = {
|
|
[REG_DR_2mA] = 2,
|
|
[REG_DR_4mA] = 4,
|
|
[REG_DR_8mA] = 8,
|
|
[REG_DR_12mA] = 12,
|
|
};
|
|
|
|
static int tz1090_pdc_pinconf_group_reg(struct pinctrl_dev *pctldev,
|
|
const struct tz1090_pdc_pingroup *g,
|
|
enum pin_config_param param,
|
|
bool report_err, u32 *reg, u32 *width,
|
|
u32 *mask, u32 *shift, const int **map)
|
|
{
|
|
/* Drive configuration applies in groups, but not to all groups. */
|
|
if (!g->drv) {
|
|
if (report_err)
|
|
dev_dbg(pctldev->dev,
|
|
"%s: group %s has no drive control\n",
|
|
__func__, g->name);
|
|
return -ENOTSUPP;
|
|
}
|
|
|
|
/* Find information about drive parameter's register */
|
|
*reg = REG_GPIO_CONTROL2;
|
|
switch (param) {
|
|
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
|
|
*shift = REG_GPIO_CONTROL2_PDC_SCHMITT_S;
|
|
*width = 1;
|
|
*map = tz1090_pdc_boolean_map;
|
|
break;
|
|
case PIN_CONFIG_DRIVE_STRENGTH:
|
|
*shift = REG_GPIO_CONTROL2_PDC_DR_S;
|
|
*width = 2;
|
|
*map = tz1090_pdc_dr_map;
|
|
break;
|
|
case PIN_CONFIG_LOW_POWER_MODE:
|
|
*shift = REG_GPIO_CONTROL2_PDC_POS_S;
|
|
*width = 1;
|
|
*map = tz1090_pdc_boolean_map;
|
|
break;
|
|
default:
|
|
return -ENOTSUPP;
|
|
};
|
|
|
|
/* Calculate field information */
|
|
*mask = (BIT(*width) - 1) << *shift;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tz1090_pdc_pinconf_group_get(struct pinctrl_dev *pctldev,
|
|
unsigned int group,
|
|
unsigned long *config)
|
|
{
|
|
struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
|
const struct tz1090_pdc_pingroup *g = &tz1090_pdc_groups[group];
|
|
enum pin_config_param param = pinconf_to_config_param(*config);
|
|
int ret, arg;
|
|
u32 reg, width, mask, shift, val;
|
|
const int *map;
|
|
|
|
/* Get register information */
|
|
ret = tz1090_pdc_pinconf_group_reg(pctldev, g, param, true,
|
|
®, &width, &mask, &shift, &map);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* Extract field from register */
|
|
val = pmx_read(pmx, reg);
|
|
arg = map[(val & mask) >> shift];
|
|
if (arg < 0)
|
|
return arg;
|
|
|
|
/* And pack config */
|
|
*config = pinconf_to_config_packed(param, arg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tz1090_pdc_pinconf_group_set(struct pinctrl_dev *pctldev,
|
|
unsigned int group,
|
|
unsigned long config)
|
|
{
|
|
struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
|
|
const struct tz1090_pdc_pingroup *g = &tz1090_pdc_groups[group];
|
|
enum pin_config_param param = pinconf_to_config_param(config);
|
|
const unsigned int *pit;
|
|
unsigned int i;
|
|
int ret, arg;
|
|
u32 reg, width, mask, shift, val;
|
|
unsigned long flags;
|
|
const int *map;
|
|
|
|
dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n",
|
|
__func__, g->name, config);
|
|
|
|
/* Get register information */
|
|
ret = tz1090_pdc_pinconf_group_reg(pctldev, g, param, true,
|
|
®, &width, &mask, &shift, &map);
|
|
if (ret < 0) {
|
|
/*
|
|
* Maybe we're trying to set a per-pin configuration of a group,
|
|
* so do the pins one by one. This is mainly as a convenience.
|
|
*/
|
|
for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) {
|
|
ret = tz1090_pdc_pinconf_set(pctldev, *pit, config);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* Unpack argument and map it to register value */
|
|
arg = pinconf_to_config_argument(config);
|
|
for (i = 0; i < BIT(width); ++i) {
|
|
if (map[i] == arg || (map[i] == -EINVAL && !arg)) {
|
|
/* Write register field */
|
|
__global_lock2(flags);
|
|
val = pmx_read(pmx, reg);
|
|
val &= ~mask;
|
|
val |= i << shift;
|
|
pmx_write(pmx, val, reg);
|
|
__global_unlock2(flags);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
dev_dbg(pctldev->dev, "%s: arg %u not supported\n",
|
|
__func__, arg);
|
|
return 0;
|
|
}
|
|
|
|
static struct pinconf_ops tz1090_pdc_pinconf_ops = {
|
|
.is_generic = true,
|
|
.pin_config_get = tz1090_pdc_pinconf_get,
|
|
.pin_config_set = tz1090_pdc_pinconf_set,
|
|
.pin_config_group_get = tz1090_pdc_pinconf_group_get,
|
|
.pin_config_group_set = tz1090_pdc_pinconf_group_set,
|
|
.pin_config_config_dbg_show = pinconf_generic_dump_config,
|
|
};
|
|
|
|
/*
|
|
* Pin control driver setup
|
|
*/
|
|
|
|
static struct pinctrl_desc tz1090_pdc_pinctrl_desc = {
|
|
.pctlops = &tz1090_pdc_pinctrl_ops,
|
|
.pmxops = &tz1090_pdc_pinmux_ops,
|
|
.confops = &tz1090_pdc_pinconf_ops,
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
static int tz1090_pdc_pinctrl_probe(struct platform_device *pdev)
|
|
{
|
|
struct tz1090_pdc_pmx *pmx;
|
|
struct resource *res;
|
|
|
|
pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
|
|
if (!pmx) {
|
|
dev_err(&pdev->dev, "Can't alloc tz1090_pdc_pmx\n");
|
|
return -ENOMEM;
|
|
}
|
|
pmx->dev = &pdev->dev;
|
|
spin_lock_init(&pmx->lock);
|
|
|
|
tz1090_pdc_pinctrl_desc.name = dev_name(&pdev->dev);
|
|
tz1090_pdc_pinctrl_desc.pins = tz1090_pdc_pins;
|
|
tz1090_pdc_pinctrl_desc.npins = ARRAY_SIZE(tz1090_pdc_pins);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "Missing MEM resource\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (!devm_request_mem_region(&pdev->dev, res->start,
|
|
resource_size(res),
|
|
dev_name(&pdev->dev))) {
|
|
dev_err(&pdev->dev,
|
|
"Couldn't request MEM resource\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
pmx->regs = devm_ioremap(&pdev->dev, res->start,
|
|
resource_size(res));
|
|
if (!pmx->regs) {
|
|
dev_err(&pdev->dev, "Couldn't ioremap regs\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
pmx->pctl = pinctrl_register(&tz1090_pdc_pinctrl_desc, &pdev->dev, pmx);
|
|
if (!pmx->pctl) {
|
|
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, pmx);
|
|
|
|
dev_info(&pdev->dev, "TZ1090 PDC pinctrl driver initialised\n");
|
|
|
|
return 0;
|
|
}
|
|
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static int tz1090_pdc_pinctrl_remove(struct platform_device *pdev)
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{
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struct tz1090_pdc_pmx *pmx = platform_get_drvdata(pdev);
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|
|
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pinctrl_unregister(pmx->pctl);
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|
|
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return 0;
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}
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|
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static struct of_device_id tz1090_pdc_pinctrl_of_match[] = {
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{ .compatible = "img,tz1090-pdc-pinctrl", },
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{ },
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|
};
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|
|
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static struct platform_driver tz1090_pdc_pinctrl_driver = {
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.driver = {
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.name = "tz1090-pdc-pinctrl",
|
|
.owner = THIS_MODULE,
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.of_match_table = tz1090_pdc_pinctrl_of_match,
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|
},
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.probe = tz1090_pdc_pinctrl_probe,
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.remove = tz1090_pdc_pinctrl_remove,
|
|
};
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|
|
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static int __init tz1090_pdc_pinctrl_init(void)
|
|
{
|
|
return platform_driver_register(&tz1090_pdc_pinctrl_driver);
|
|
}
|
|
arch_initcall(tz1090_pdc_pinctrl_init);
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|
|
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static void __exit tz1090_pdc_pinctrl_exit(void)
|
|
{
|
|
platform_driver_unregister(&tz1090_pdc_pinctrl_driver);
|
|
}
|
|
module_exit(tz1090_pdc_pinctrl_exit);
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|
|
|
MODULE_AUTHOR("Imagination Technologies Ltd.");
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|
MODULE_DESCRIPTION("Toumaz Xenif TZ1090 PDC pinctrl driver");
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|
MODULE_LICENSE("GPL v2");
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MODULE_DEVICE_TABLE(of, tz1090_pdc_pinctrl_of_match);
|