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55668611d0
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
256 lines
8.2 KiB
C
256 lines
8.2 KiB
C
/****************************************************************************
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* Driver for Solarflare Solarstorm network controllers and boards
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* Copyright 2005-2006 Fen Systems Ltd.
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* Copyright 2006-2008 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#ifndef EFX_FALCON_IO_H
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#define EFX_FALCON_IO_H
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include "net_driver.h"
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/**************************************************************************
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*
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* Falcon hardware access
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*
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**************************************************************************
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*
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* Notes on locking strategy:
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*
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* Most Falcon registers require 16-byte (or 8-byte, for SRAM
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* registers) atomic writes which necessitates locking.
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* Under normal operation few writes to the Falcon BAR are made and these
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* registers (EVQ_RPTR_REG, RX_DESC_UPD_REG and TX_DESC_UPD_REG) are special
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* cased to allow 4-byte (hence lockless) accesses.
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*
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* It *is* safe to write to these 4-byte registers in the middle of an
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* access to an 8-byte or 16-byte register. We therefore use a
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* spinlock to protect accesses to the larger registers, but no locks
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* for the 4-byte registers.
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*
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* A write barrier is needed to ensure that DW3 is written after DW0/1/2
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* due to the way the 16byte registers are "collected" in the Falcon BIU
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*
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* We also lock when carrying out reads, to ensure consistency of the
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* data (made possible since the BIU reads all 128 bits into a cache).
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* Reads are very rare, so this isn't a significant performance
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* impact. (Most data transferred from NIC to host is DMAed directly
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* into host memory).
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*
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* I/O BAR access uses locks for both reads and writes (but is only provided
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* for testing purposes).
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*/
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/* Special buffer descriptors (Falcon SRAM) */
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#define BUF_TBL_KER_A1 0x18000
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#define BUF_TBL_KER_B0 0x800000
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#if BITS_PER_LONG == 64
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#define FALCON_USE_QWORD_IO 1
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#endif
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#ifdef FALCON_USE_QWORD_IO
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static inline void _falcon_writeq(struct efx_nic *efx, __le64 value,
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unsigned int reg)
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{
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__raw_writeq((__force u64)value, efx->membase + reg);
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}
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static inline __le64 _falcon_readq(struct efx_nic *efx, unsigned int reg)
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{
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return (__force __le64)__raw_readq(efx->membase + reg);
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}
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#endif
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static inline void _falcon_writel(struct efx_nic *efx, __le32 value,
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unsigned int reg)
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{
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__raw_writel((__force u32)value, efx->membase + reg);
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}
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static inline __le32 _falcon_readl(struct efx_nic *efx, unsigned int reg)
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{
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return (__force __le32)__raw_readl(efx->membase + reg);
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}
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/* Writes to a normal 16-byte Falcon register, locking as appropriate. */
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static inline void falcon_write(struct efx_nic *efx, efx_oword_t *value,
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unsigned int reg)
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{
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unsigned long flags;
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EFX_REGDUMP(efx, "writing register %x with " EFX_OWORD_FMT "\n", reg,
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EFX_OWORD_VAL(*value));
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spin_lock_irqsave(&efx->biu_lock, flags);
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#ifdef FALCON_USE_QWORD_IO
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_falcon_writeq(efx, value->u64[0], reg + 0);
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wmb();
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_falcon_writeq(efx, value->u64[1], reg + 8);
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#else
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_falcon_writel(efx, value->u32[0], reg + 0);
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_falcon_writel(efx, value->u32[1], reg + 4);
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_falcon_writel(efx, value->u32[2], reg + 8);
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wmb();
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_falcon_writel(efx, value->u32[3], reg + 12);
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#endif
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mmiowb();
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spin_unlock_irqrestore(&efx->biu_lock, flags);
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}
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/* Writes to an 8-byte Falcon SRAM register, locking as appropriate. */
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static inline void falcon_write_sram(struct efx_nic *efx, efx_qword_t *value,
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unsigned int index)
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{
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unsigned int reg = efx->type->buf_tbl_base + (index * sizeof(*value));
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unsigned long flags;
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EFX_REGDUMP(efx, "writing SRAM register %x with " EFX_QWORD_FMT "\n",
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reg, EFX_QWORD_VAL(*value));
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spin_lock_irqsave(&efx->biu_lock, flags);
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#ifdef FALCON_USE_QWORD_IO
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_falcon_writeq(efx, value->u64[0], reg + 0);
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#else
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_falcon_writel(efx, value->u32[0], reg + 0);
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wmb();
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_falcon_writel(efx, value->u32[1], reg + 4);
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#endif
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mmiowb();
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spin_unlock_irqrestore(&efx->biu_lock, flags);
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}
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/* Write dword to Falcon register that allows partial writes
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*
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* Some Falcon registers (EVQ_RPTR_REG, RX_DESC_UPD_REG and
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* TX_DESC_UPD_REG) can be written to as a single dword. This allows
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* for lockless writes.
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*/
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static inline void falcon_writel(struct efx_nic *efx, efx_dword_t *value,
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unsigned int reg)
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{
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EFX_REGDUMP(efx, "writing partial register %x with "EFX_DWORD_FMT"\n",
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reg, EFX_DWORD_VAL(*value));
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/* No lock required */
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_falcon_writel(efx, value->u32[0], reg);
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}
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/* Read from a Falcon register
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*
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* This reads an entire 16-byte Falcon register in one go, locking as
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* appropriate. It is essential to read the first dword first, as this
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* prompts Falcon to load the current value into the shadow register.
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*/
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static inline void falcon_read(struct efx_nic *efx, efx_oword_t *value,
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unsigned int reg)
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{
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unsigned long flags;
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spin_lock_irqsave(&efx->biu_lock, flags);
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value->u32[0] = _falcon_readl(efx, reg + 0);
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rmb();
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value->u32[1] = _falcon_readl(efx, reg + 4);
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value->u32[2] = _falcon_readl(efx, reg + 8);
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value->u32[3] = _falcon_readl(efx, reg + 12);
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spin_unlock_irqrestore(&efx->biu_lock, flags);
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EFX_REGDUMP(efx, "read from register %x, got " EFX_OWORD_FMT "\n", reg,
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EFX_OWORD_VAL(*value));
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}
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/* This reads an 8-byte Falcon SRAM entry in one go. */
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static inline void falcon_read_sram(struct efx_nic *efx, efx_qword_t *value,
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unsigned int index)
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{
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unsigned int reg = efx->type->buf_tbl_base + (index * sizeof(*value));
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unsigned long flags;
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spin_lock_irqsave(&efx->biu_lock, flags);
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#ifdef FALCON_USE_QWORD_IO
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value->u64[0] = _falcon_readq(efx, reg + 0);
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#else
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value->u32[0] = _falcon_readl(efx, reg + 0);
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rmb();
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value->u32[1] = _falcon_readl(efx, reg + 4);
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#endif
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spin_unlock_irqrestore(&efx->biu_lock, flags);
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EFX_REGDUMP(efx, "read from SRAM register %x, got "EFX_QWORD_FMT"\n",
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reg, EFX_QWORD_VAL(*value));
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}
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/* Read dword from Falcon register that allows partial writes (sic) */
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static inline void falcon_readl(struct efx_nic *efx, efx_dword_t *value,
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unsigned int reg)
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{
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value->u32[0] = _falcon_readl(efx, reg);
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EFX_REGDUMP(efx, "read from register %x, got "EFX_DWORD_FMT"\n",
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reg, EFX_DWORD_VAL(*value));
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}
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/* Write to a register forming part of a table */
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static inline void falcon_write_table(struct efx_nic *efx, efx_oword_t *value,
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unsigned int reg, unsigned int index)
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{
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falcon_write(efx, value, reg + index * sizeof(efx_oword_t));
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}
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/* Read to a register forming part of a table */
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static inline void falcon_read_table(struct efx_nic *efx, efx_oword_t *value,
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unsigned int reg, unsigned int index)
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{
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falcon_read(efx, value, reg + index * sizeof(efx_oword_t));
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}
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/* Write to a dword register forming part of a table */
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static inline void falcon_writel_table(struct efx_nic *efx, efx_dword_t *value,
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unsigned int reg, unsigned int index)
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{
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falcon_writel(efx, value, reg + index * sizeof(efx_oword_t));
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}
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/* Page-mapped register block size */
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#define FALCON_PAGE_BLOCK_SIZE 0x2000
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/* Calculate offset to page-mapped register block */
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#define FALCON_PAGED_REG(page, reg) \
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((page) * FALCON_PAGE_BLOCK_SIZE + (reg))
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/* As for falcon_write(), but for a page-mapped register. */
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static inline void falcon_write_page(struct efx_nic *efx, efx_oword_t *value,
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unsigned int reg, unsigned int page)
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{
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falcon_write(efx, value, FALCON_PAGED_REG(page, reg));
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}
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/* As for falcon_writel(), but for a page-mapped register. */
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static inline void falcon_writel_page(struct efx_nic *efx, efx_dword_t *value,
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unsigned int reg, unsigned int page)
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{
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falcon_writel(efx, value, FALCON_PAGED_REG(page, reg));
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}
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/* Write dword to Falcon page-mapped register with an extra lock.
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*
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* As for falcon_writel_page(), but for a register that suffers from
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* SFC bug 3181. Take out a lock so the BIU collector cannot be
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* confused. */
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static inline void falcon_writel_page_locked(struct efx_nic *efx,
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efx_dword_t *value,
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unsigned int reg,
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unsigned int page)
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{
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unsigned long flags;
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spin_lock_irqsave(&efx->biu_lock, flags);
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falcon_writel(efx, value, FALCON_PAGED_REG(page, reg));
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spin_unlock_irqrestore(&efx->biu_lock, flags);
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}
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#endif /* EFX_FALCON_IO_H */
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