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f8ae2d2919
Both snd_vx_hardware and snd_vx_ops are only referred without modification, hence they can be constified gracefully for further optimizations. There should be no functional changes by this patch. Link: https://lore.kernel.org/r/20200103081714.9560-31-tiwai@suse.de Signed-off-by: Takashi Iwai <tiwai@suse.de>
103 lines
3.6 KiB
C
103 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Driver for Digigram VX222 PCI soundcards
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*
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* Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
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*/
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#ifndef __VX222_H
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#define __VX222_H
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#include <sound/vx_core.h>
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struct snd_vx222 {
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struct vx_core core;
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/* h/w config; for PLX and for DSP */
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struct pci_dev *pci;
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unsigned long port[2];
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unsigned int regCDSP; /* current CDSP register */
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unsigned int regCFG; /* current CFG register */
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unsigned int regSELMIC; /* current SELMIC reg. (for VX222 Mic) */
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int input_level[2]; /* input level for vx222 mic */
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int mic_level; /* mic level for vx222 mic */
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};
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#define to_vx222(x) container_of(x, struct snd_vx222, core)
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/* we use a lookup table with 148 values, see vx_mixer.c */
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#define VX2_AKM_LEVEL_MAX 0x93
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extern const struct snd_vx_ops vx222_ops;
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extern const struct snd_vx_ops vx222_old_ops;
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/* Offset of registers with base equal to portDSP. */
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#define VX_RESET_DMA_REGISTER_OFFSET 0x00000008
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/* Constants used to access the INTCSR register. */
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#define VX_INTCSR_VALUE 0x00000001
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#define VX_PCI_INTERRUPT_MASK 0x00000040
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/* Constants used to access the CDSP register (0x20). */
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#define VX_CDSP_TEST1_MASK 0x00000080
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#define VX_CDSP_TOR1_MASK 0x00000040
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#define VX_CDSP_TOR2_MASK 0x00000020
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#define VX_CDSP_RESERVED0_0_MASK 0x00000010
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#define VX_CDSP_CODEC_RESET_MASK 0x00000008
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#define VX_CDSP_VALID_IRQ_MASK 0x00000004
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#define VX_CDSP_TEST0_MASK 0x00000002
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#define VX_CDSP_DSP_RESET_MASK 0x00000001
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#define VX_CDSP_GPIO_OUT_MASK 0x00000060
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#define VX_GPIO_OUT_BIT_OFFSET 5 // transform output to bit 0 and 1
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/* Constants used to access the CFG register (0x24). */
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#define VX_CFG_SYNCDSP_MASK 0x00000080
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#define VX_CFG_RESERVED0_0_MASK 0x00000040
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#define VX_CFG_RESERVED1_0_MASK 0x00000020
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#define VX_CFG_RESERVED2_0_MASK 0x00000010
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#define VX_CFG_DATAIN_SEL_MASK 0x00000008 // 0 (ana), 1 (UER)
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#define VX_CFG_RESERVED3_0_MASK 0x00000004
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#define VX_CFG_RESERVED4_0_MASK 0x00000002
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#define VX_CFG_CLOCKIN_SEL_MASK 0x00000001 // 0 (internal), 1 (AES/EBU)
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/* Constants used to access the STATUS register (0x30). */
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#define VX_STATUS_DATA_XICOR_MASK 0x00000080
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#define VX_STATUS_VAL_TEST1_MASK 0x00000040
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#define VX_STATUS_VAL_TEST0_MASK 0x00000020
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#define VX_STATUS_RESERVED0_MASK 0x00000010
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#define VX_STATUS_VAL_TOR1_MASK 0x00000008
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#define VX_STATUS_VAL_TOR0_MASK 0x00000004
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#define VX_STATUS_LEVEL_IN_MASK 0x00000002 // 6 dBu (0), 22 dBu (1)
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#define VX_STATUS_MEMIRQ_MASK 0x00000001
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#define VX_STATUS_GPIO_IN_MASK 0x0000000C
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#define VX_GPIO_IN_BIT_OFFSET 0 // leave input as bit 2 and 3
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/* Constants used to access the MICRO INPUT SELECT register (0x40). */
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#define MICRO_SELECT_INPUT_NORM 0x00
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#define MICRO_SELECT_INPUT_MUTE 0x01
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#define MICRO_SELECT_INPUT_LIMIT 0x02
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#define MICRO_SELECT_INPUT_MASK 0x03
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#define MICRO_SELECT_PREAMPLI_G_0 0x00
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#define MICRO_SELECT_PREAMPLI_G_1 0x04
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#define MICRO_SELECT_PREAMPLI_G_2 0x08
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#define MICRO_SELECT_PREAMPLI_G_3 0x0C
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#define MICRO_SELECT_PREAMPLI_MASK 0x0C
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#define MICRO_SELECT_PREAMPLI_OFFSET 2
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#define MICRO_SELECT_RAISE_COMPR 0x10
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#define MICRO_SELECT_NOISE_T_52DB 0x00
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#define MICRO_SELECT_NOISE_T_42DB 0x20
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#define MICRO_SELECT_NOISE_T_32DB 0x40
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#define MICRO_SELECT_NOISE_T_MASK 0x60
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#define MICRO_SELECT_PHANTOM_ALIM 0x80
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#endif /* __VX222_H */
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