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![Thomas Gleixner](/assets/img/avatar_default.png)
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
513 lines
11 KiB
C
513 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Driver for 93xx46 EEPROMs
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*
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* (C) 2011 DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/gpio/consumer.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
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#include <linux/nvmem-provider.h>
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#include <linux/eeprom_93xx46.h>
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#define OP_START 0x4
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#define OP_WRITE (OP_START | 0x1)
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#define OP_READ (OP_START | 0x2)
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#define ADDR_EWDS 0x00
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#define ADDR_ERAL 0x20
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#define ADDR_EWEN 0x30
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struct eeprom_93xx46_devtype_data {
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unsigned int quirks;
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};
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static const struct eeprom_93xx46_devtype_data atmel_at93c46d_data = {
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.quirks = EEPROM_93XX46_QUIRK_SINGLE_WORD_READ |
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EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH,
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};
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struct eeprom_93xx46_dev {
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struct spi_device *spi;
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struct eeprom_93xx46_platform_data *pdata;
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struct mutex lock;
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struct nvmem_config nvmem_config;
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struct nvmem_device *nvmem;
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int addrlen;
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int size;
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};
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static inline bool has_quirk_single_word_read(struct eeprom_93xx46_dev *edev)
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{
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return edev->pdata->quirks & EEPROM_93XX46_QUIRK_SINGLE_WORD_READ;
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}
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static inline bool has_quirk_instruction_length(struct eeprom_93xx46_dev *edev)
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{
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return edev->pdata->quirks & EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH;
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}
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static int eeprom_93xx46_read(void *priv, unsigned int off,
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void *val, size_t count)
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{
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struct eeprom_93xx46_dev *edev = priv;
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char *buf = val;
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int err = 0;
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if (unlikely(off >= edev->size))
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return 0;
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if ((off + count) > edev->size)
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count = edev->size - off;
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if (unlikely(!count))
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return count;
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mutex_lock(&edev->lock);
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if (edev->pdata->prepare)
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edev->pdata->prepare(edev);
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while (count) {
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struct spi_message m;
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struct spi_transfer t[2] = { { 0 } };
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u16 cmd_addr = OP_READ << edev->addrlen;
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size_t nbytes = count;
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int bits;
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if (edev->addrlen == 7) {
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cmd_addr |= off & 0x7f;
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bits = 10;
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if (has_quirk_single_word_read(edev))
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nbytes = 1;
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} else {
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cmd_addr |= (off >> 1) & 0x3f;
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bits = 9;
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if (has_quirk_single_word_read(edev))
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nbytes = 2;
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}
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dev_dbg(&edev->spi->dev, "read cmd 0x%x, %d Hz\n",
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cmd_addr, edev->spi->max_speed_hz);
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spi_message_init(&m);
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t[0].tx_buf = (char *)&cmd_addr;
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t[0].len = 2;
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t[0].bits_per_word = bits;
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spi_message_add_tail(&t[0], &m);
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t[1].rx_buf = buf;
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t[1].len = count;
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t[1].bits_per_word = 8;
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spi_message_add_tail(&t[1], &m);
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err = spi_sync(edev->spi, &m);
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/* have to wait at least Tcsl ns */
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ndelay(250);
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if (err) {
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dev_err(&edev->spi->dev, "read %zu bytes at %d: err. %d\n",
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nbytes, (int)off, err);
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break;
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}
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buf += nbytes;
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off += nbytes;
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count -= nbytes;
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}
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if (edev->pdata->finish)
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edev->pdata->finish(edev);
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mutex_unlock(&edev->lock);
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return err;
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}
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static int eeprom_93xx46_ew(struct eeprom_93xx46_dev *edev, int is_on)
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{
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struct spi_message m;
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struct spi_transfer t;
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int bits, ret;
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u16 cmd_addr;
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cmd_addr = OP_START << edev->addrlen;
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if (edev->addrlen == 7) {
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cmd_addr |= (is_on ? ADDR_EWEN : ADDR_EWDS) << 1;
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bits = 10;
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} else {
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cmd_addr |= (is_on ? ADDR_EWEN : ADDR_EWDS);
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bits = 9;
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}
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if (has_quirk_instruction_length(edev)) {
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cmd_addr <<= 2;
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bits += 2;
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}
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dev_dbg(&edev->spi->dev, "ew%s cmd 0x%04x, %d bits\n",
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is_on ? "en" : "ds", cmd_addr, bits);
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spi_message_init(&m);
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memset(&t, 0, sizeof(t));
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t.tx_buf = &cmd_addr;
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t.len = 2;
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t.bits_per_word = bits;
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spi_message_add_tail(&t, &m);
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mutex_lock(&edev->lock);
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if (edev->pdata->prepare)
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edev->pdata->prepare(edev);
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ret = spi_sync(edev->spi, &m);
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/* have to wait at least Tcsl ns */
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ndelay(250);
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if (ret)
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dev_err(&edev->spi->dev, "erase/write %sable error %d\n",
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is_on ? "en" : "dis", ret);
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if (edev->pdata->finish)
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edev->pdata->finish(edev);
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mutex_unlock(&edev->lock);
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return ret;
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}
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static ssize_t
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eeprom_93xx46_write_word(struct eeprom_93xx46_dev *edev,
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const char *buf, unsigned off)
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{
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struct spi_message m;
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struct spi_transfer t[2];
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int bits, data_len, ret;
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u16 cmd_addr;
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cmd_addr = OP_WRITE << edev->addrlen;
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if (edev->addrlen == 7) {
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cmd_addr |= off & 0x7f;
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bits = 10;
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data_len = 1;
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} else {
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cmd_addr |= (off >> 1) & 0x3f;
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bits = 9;
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data_len = 2;
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}
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dev_dbg(&edev->spi->dev, "write cmd 0x%x\n", cmd_addr);
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spi_message_init(&m);
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memset(t, 0, sizeof(t));
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t[0].tx_buf = (char *)&cmd_addr;
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t[0].len = 2;
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t[0].bits_per_word = bits;
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spi_message_add_tail(&t[0], &m);
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t[1].tx_buf = buf;
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t[1].len = data_len;
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t[1].bits_per_word = 8;
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spi_message_add_tail(&t[1], &m);
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ret = spi_sync(edev->spi, &m);
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/* have to wait program cycle time Twc ms */
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mdelay(6);
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return ret;
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}
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static int eeprom_93xx46_write(void *priv, unsigned int off,
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void *val, size_t count)
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{
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struct eeprom_93xx46_dev *edev = priv;
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char *buf = val;
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int i, ret, step = 1;
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if (unlikely(off >= edev->size))
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return -EFBIG;
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if ((off + count) > edev->size)
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count = edev->size - off;
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if (unlikely(!count))
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return count;
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/* only write even number of bytes on 16-bit devices */
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if (edev->addrlen == 6) {
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step = 2;
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count &= ~1;
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}
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/* erase/write enable */
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ret = eeprom_93xx46_ew(edev, 1);
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if (ret)
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return ret;
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mutex_lock(&edev->lock);
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if (edev->pdata->prepare)
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edev->pdata->prepare(edev);
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for (i = 0; i < count; i += step) {
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ret = eeprom_93xx46_write_word(edev, &buf[i], off + i);
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if (ret) {
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dev_err(&edev->spi->dev, "write failed at %d: %d\n",
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(int)off + i, ret);
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break;
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}
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}
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if (edev->pdata->finish)
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edev->pdata->finish(edev);
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mutex_unlock(&edev->lock);
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/* erase/write disable */
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eeprom_93xx46_ew(edev, 0);
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return ret;
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}
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static int eeprom_93xx46_eral(struct eeprom_93xx46_dev *edev)
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{
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struct eeprom_93xx46_platform_data *pd = edev->pdata;
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struct spi_message m;
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struct spi_transfer t;
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int bits, ret;
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u16 cmd_addr;
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cmd_addr = OP_START << edev->addrlen;
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if (edev->addrlen == 7) {
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cmd_addr |= ADDR_ERAL << 1;
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bits = 10;
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} else {
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cmd_addr |= ADDR_ERAL;
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bits = 9;
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}
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if (has_quirk_instruction_length(edev)) {
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cmd_addr <<= 2;
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bits += 2;
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}
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dev_dbg(&edev->spi->dev, "eral cmd 0x%04x, %d bits\n", cmd_addr, bits);
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spi_message_init(&m);
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memset(&t, 0, sizeof(t));
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t.tx_buf = &cmd_addr;
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t.len = 2;
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t.bits_per_word = bits;
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spi_message_add_tail(&t, &m);
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mutex_lock(&edev->lock);
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if (edev->pdata->prepare)
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edev->pdata->prepare(edev);
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ret = spi_sync(edev->spi, &m);
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if (ret)
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dev_err(&edev->spi->dev, "erase error %d\n", ret);
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/* have to wait erase cycle time Tec ms */
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mdelay(6);
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if (pd->finish)
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pd->finish(edev);
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mutex_unlock(&edev->lock);
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return ret;
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}
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static ssize_t eeprom_93xx46_store_erase(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct eeprom_93xx46_dev *edev = dev_get_drvdata(dev);
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int erase = 0, ret;
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sscanf(buf, "%d", &erase);
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if (erase) {
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ret = eeprom_93xx46_ew(edev, 1);
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if (ret)
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return ret;
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ret = eeprom_93xx46_eral(edev);
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if (ret)
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return ret;
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ret = eeprom_93xx46_ew(edev, 0);
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if (ret)
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return ret;
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}
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return count;
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}
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static DEVICE_ATTR(erase, S_IWUSR, NULL, eeprom_93xx46_store_erase);
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static void select_assert(void *context)
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{
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struct eeprom_93xx46_dev *edev = context;
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gpiod_set_value_cansleep(edev->pdata->select, 1);
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}
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static void select_deassert(void *context)
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{
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struct eeprom_93xx46_dev *edev = context;
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gpiod_set_value_cansleep(edev->pdata->select, 0);
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}
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static const struct of_device_id eeprom_93xx46_of_table[] = {
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{ .compatible = "eeprom-93xx46", },
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{ .compatible = "atmel,at93c46d", .data = &atmel_at93c46d_data, },
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{}
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};
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MODULE_DEVICE_TABLE(of, eeprom_93xx46_of_table);
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static int eeprom_93xx46_probe_dt(struct spi_device *spi)
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{
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const struct of_device_id *of_id =
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of_match_device(eeprom_93xx46_of_table, &spi->dev);
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struct device_node *np = spi->dev.of_node;
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struct eeprom_93xx46_platform_data *pd;
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u32 tmp;
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int ret;
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pd = devm_kzalloc(&spi->dev, sizeof(*pd), GFP_KERNEL);
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if (!pd)
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return -ENOMEM;
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ret = of_property_read_u32(np, "data-size", &tmp);
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if (ret < 0) {
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dev_err(&spi->dev, "data-size property not found\n");
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return ret;
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}
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if (tmp == 8) {
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pd->flags |= EE_ADDR8;
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} else if (tmp == 16) {
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pd->flags |= EE_ADDR16;
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} else {
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dev_err(&spi->dev, "invalid data-size (%d)\n", tmp);
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return -EINVAL;
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}
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if (of_property_read_bool(np, "read-only"))
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pd->flags |= EE_READONLY;
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pd->select = devm_gpiod_get_optional(&spi->dev, "select",
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GPIOD_OUT_LOW);
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if (IS_ERR(pd->select))
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return PTR_ERR(pd->select);
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pd->prepare = select_assert;
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pd->finish = select_deassert;
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gpiod_direction_output(pd->select, 0);
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if (of_id->data) {
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const struct eeprom_93xx46_devtype_data *data = of_id->data;
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pd->quirks = data->quirks;
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}
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spi->dev.platform_data = pd;
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return 0;
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}
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static int eeprom_93xx46_probe(struct spi_device *spi)
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{
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struct eeprom_93xx46_platform_data *pd;
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struct eeprom_93xx46_dev *edev;
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int err;
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if (spi->dev.of_node) {
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err = eeprom_93xx46_probe_dt(spi);
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if (err < 0)
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return err;
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}
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pd = spi->dev.platform_data;
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if (!pd) {
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dev_err(&spi->dev, "missing platform data\n");
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return -ENODEV;
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}
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edev = devm_kzalloc(&spi->dev, sizeof(*edev), GFP_KERNEL);
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if (!edev)
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return -ENOMEM;
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if (pd->flags & EE_ADDR8)
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edev->addrlen = 7;
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else if (pd->flags & EE_ADDR16)
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edev->addrlen = 6;
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else {
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dev_err(&spi->dev, "unspecified address type\n");
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return -EINVAL;
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}
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mutex_init(&edev->lock);
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edev->spi = spi;
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edev->pdata = pd;
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edev->size = 128;
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edev->nvmem_config.name = dev_name(&spi->dev);
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edev->nvmem_config.dev = &spi->dev;
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edev->nvmem_config.read_only = pd->flags & EE_READONLY;
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edev->nvmem_config.root_only = true;
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edev->nvmem_config.owner = THIS_MODULE;
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edev->nvmem_config.compat = true;
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edev->nvmem_config.base_dev = &spi->dev;
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edev->nvmem_config.reg_read = eeprom_93xx46_read;
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edev->nvmem_config.reg_write = eeprom_93xx46_write;
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edev->nvmem_config.priv = edev;
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edev->nvmem_config.stride = 4;
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edev->nvmem_config.word_size = 1;
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edev->nvmem_config.size = edev->size;
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edev->nvmem = devm_nvmem_register(&spi->dev, &edev->nvmem_config);
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if (IS_ERR(edev->nvmem))
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return PTR_ERR(edev->nvmem);
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dev_info(&spi->dev, "%d-bit eeprom %s\n",
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(pd->flags & EE_ADDR8) ? 8 : 16,
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(pd->flags & EE_READONLY) ? "(readonly)" : "");
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if (!(pd->flags & EE_READONLY)) {
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if (device_create_file(&spi->dev, &dev_attr_erase))
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dev_err(&spi->dev, "can't create erase interface\n");
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}
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spi_set_drvdata(spi, edev);
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return 0;
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}
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static int eeprom_93xx46_remove(struct spi_device *spi)
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{
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struct eeprom_93xx46_dev *edev = spi_get_drvdata(spi);
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if (!(edev->pdata->flags & EE_READONLY))
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device_remove_file(&spi->dev, &dev_attr_erase);
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return 0;
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}
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static struct spi_driver eeprom_93xx46_driver = {
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.driver = {
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.name = "93xx46",
|
|
.of_match_table = of_match_ptr(eeprom_93xx46_of_table),
|
|
},
|
|
.probe = eeprom_93xx46_probe,
|
|
.remove = eeprom_93xx46_remove,
|
|
};
|
|
|
|
module_spi_driver(eeprom_93xx46_driver);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("Driver for 93xx46 EEPROMs");
|
|
MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
|
|
MODULE_ALIAS("spi:93xx46");
|