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The AST2600 pinmux is fairly similar to the previous generations of ASPEED BMC SoCs in terms of architecture, though differ in some of the design details. The complexity of the pin expressions is largely reduced (e.g. there are no-longer signals with multiple expressions muxing them to the associated pin), and there are now signals and buses with multiple pin groups. The driver implements pinmux support for all 244 GPIO-capable pins plus a further four pins that are not GPIO capable but which expose multiple signals. pinconf will be implemented in a follow-up patch. The implementation has been smoke-tested under qemu, and run on hardware by ASPEED. Debugged-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20190711041942.23202-7-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
33 lines
1,018 B
Text
33 lines
1,018 B
Text
# SPDX-License-Identifier: GPL-2.0-only
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config PINCTRL_ASPEED
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bool
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depends on (ARCH_ASPEED || COMPILE_TEST) && OF
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depends on MFD_SYSCON
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select PINMUX
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select PINCONF
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select GENERIC_PINCONF
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select REGMAP_MMIO
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config PINCTRL_ASPEED_G4
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bool "Aspeed G4 SoC pin control"
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depends on (MACH_ASPEED_G4 || COMPILE_TEST) && OF
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select PINCTRL_ASPEED
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help
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Say Y here to enable pin controller support for Aspeed's 4th
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generation SoCs. GPIO is provided by a separate GPIO driver.
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config PINCTRL_ASPEED_G5
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bool "Aspeed G5 SoC pin control"
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depends on (MACH_ASPEED_G5 || COMPILE_TEST) && OF
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select PINCTRL_ASPEED
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help
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Say Y here to enable pin controller support for Aspeed's 5th
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generation SoCs. GPIO is provided by a separate GPIO driver.
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config PINCTRL_ASPEED_G6
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bool "Aspeed G6 SoC pin control"
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depends on (MACH_ASPEED_G6 || COMPILE_TEST) && OF
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select PINCTRL_ASPEED
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help
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Say Y here to enable pin controller support for Aspeed's 6th
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generation SoCs. GPIO is provided by a separate GPIO driver.
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