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5c8d08f347
Add definitions for the Tegra20+ memory controller hot resets. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
21 lines
616 B
C
21 lines
616 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef DT_BINDINGS_MEMORY_TEGRA20_MC_H
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#define DT_BINDINGS_MEMORY_TEGRA20_MC_H
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#define TEGRA20_MC_RESET_AVPC 0
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#define TEGRA20_MC_RESET_DC 1
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#define TEGRA20_MC_RESET_DCB 2
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#define TEGRA20_MC_RESET_EPP 3
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#define TEGRA20_MC_RESET_2D 4
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#define TEGRA20_MC_RESET_HC 5
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#define TEGRA20_MC_RESET_ISP 6
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#define TEGRA20_MC_RESET_MPCORE 7
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#define TEGRA20_MC_RESET_MPEA 8
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#define TEGRA20_MC_RESET_MPEB 9
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#define TEGRA20_MC_RESET_MPEC 10
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#define TEGRA20_MC_RESET_3D 11
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#define TEGRA20_MC_RESET_PPCS 12
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#define TEGRA20_MC_RESET_VDE 13
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#define TEGRA20_MC_RESET_VI 14
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#endif
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