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![Tejun Heo](/assets/img/avatar_default.png)
percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
523 lines
12 KiB
C
523 lines
12 KiB
C
/*
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* Intel X38 Memory Controller kernel module
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* Copyright (C) 2008 Cluster Computing, Inc.
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*
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* This file may be distributed under the terms of the
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* GNU General Public License.
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*
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* This file is based on i3200_edac.c
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*
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <linux/edac.h>
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#include "edac_core.h"
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#define X38_REVISION "1.1"
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#define EDAC_MOD_STR "x38_edac"
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#define PCI_DEVICE_ID_INTEL_X38_HB 0x29e0
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#define X38_RANKS 8
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#define X38_RANKS_PER_CHANNEL 4
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#define X38_CHANNELS 2
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/* Intel X38 register addresses - device 0 function 0 - DRAM Controller */
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#define X38_MCHBAR_LOW 0x48 /* MCH Memory Mapped Register BAR */
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#define X38_MCHBAR_HIGH 0x4c
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#define X38_MCHBAR_MASK 0xfffffc000ULL /* bits 35:14 */
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#define X38_MMR_WINDOW_SIZE 16384
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#define X38_TOM 0xa0 /* Top of Memory (16b)
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*
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* 15:10 reserved
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* 9:0 total populated physical memory
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*/
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#define X38_TOM_MASK 0x3ff /* bits 9:0 */
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#define X38_TOM_SHIFT 26 /* 64MiB grain */
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#define X38_ERRSTS 0xc8 /* Error Status Register (16b)
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*
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* 15 reserved
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* 14 Isochronous TBWRR Run Behind FIFO Full
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* (ITCV)
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* 13 Isochronous TBWRR Run Behind FIFO Put
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* (ITSTV)
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* 12 reserved
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* 11 MCH Thermal Sensor Event
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* for SMI/SCI/SERR (GTSE)
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* 10 reserved
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* 9 LOCK to non-DRAM Memory Flag (LCKF)
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* 8 reserved
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* 7 DRAM Throttle Flag (DTF)
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* 6:2 reserved
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* 1 Multi-bit DRAM ECC Error Flag (DMERR)
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* 0 Single-bit DRAM ECC Error Flag (DSERR)
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*/
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#define X38_ERRSTS_UE 0x0002
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#define X38_ERRSTS_CE 0x0001
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#define X38_ERRSTS_BITS (X38_ERRSTS_UE | X38_ERRSTS_CE)
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/* Intel MMIO register space - device 0 function 0 - MMR space */
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#define X38_C0DRB 0x200 /* Channel 0 DRAM Rank Boundary (16b x 4)
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*
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* 15:10 reserved
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* 9:0 Channel 0 DRAM Rank Boundary Address
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*/
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#define X38_C1DRB 0x600 /* Channel 1 DRAM Rank Boundary (16b x 4) */
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#define X38_DRB_MASK 0x3ff /* bits 9:0 */
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#define X38_DRB_SHIFT 26 /* 64MiB grain */
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#define X38_C0ECCERRLOG 0x280 /* Channel 0 ECC Error Log (64b)
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*
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* 63:48 Error Column Address (ERRCOL)
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* 47:32 Error Row Address (ERRROW)
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* 31:29 Error Bank Address (ERRBANK)
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* 28:27 Error Rank Address (ERRRANK)
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* 26:24 reserved
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* 23:16 Error Syndrome (ERRSYND)
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* 15: 2 reserved
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* 1 Multiple Bit Error Status (MERRSTS)
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* 0 Correctable Error Status (CERRSTS)
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*/
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#define X38_C1ECCERRLOG 0x680 /* Channel 1 ECC Error Log (64b) */
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#define X38_ECCERRLOG_CE 0x1
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#define X38_ECCERRLOG_UE 0x2
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#define X38_ECCERRLOG_RANK_BITS 0x18000000
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#define X38_ECCERRLOG_SYNDROME_BITS 0xff0000
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#define X38_CAPID0 0xe0 /* see P.94 of spec for details */
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static int x38_channel_num;
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static int how_many_channel(struct pci_dev *pdev)
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{
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unsigned char capid0_8b; /* 8th byte of CAPID0 */
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pci_read_config_byte(pdev, X38_CAPID0 + 8, &capid0_8b);
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if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */
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debugf0("In single channel mode.\n");
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x38_channel_num = 1;
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} else {
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debugf0("In dual channel mode.\n");
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x38_channel_num = 2;
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}
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return x38_channel_num;
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}
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static unsigned long eccerrlog_syndrome(u64 log)
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{
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return (log & X38_ECCERRLOG_SYNDROME_BITS) >> 16;
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}
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static int eccerrlog_row(int channel, u64 log)
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{
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return ((log & X38_ECCERRLOG_RANK_BITS) >> 27) |
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(channel * X38_RANKS_PER_CHANNEL);
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}
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enum x38_chips {
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X38 = 0,
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};
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struct x38_dev_info {
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const char *ctl_name;
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};
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struct x38_error_info {
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u16 errsts;
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u16 errsts2;
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u64 eccerrlog[X38_CHANNELS];
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};
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static const struct x38_dev_info x38_devs[] = {
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[X38] = {
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.ctl_name = "x38"},
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};
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static struct pci_dev *mci_pdev;
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static int x38_registered = 1;
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static void x38_clear_error_info(struct mem_ctl_info *mci)
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{
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struct pci_dev *pdev;
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pdev = to_pci_dev(mci->dev);
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/*
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* Clear any error bits.
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* (Yes, we really clear bits by writing 1 to them.)
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*/
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pci_write_bits16(pdev, X38_ERRSTS, X38_ERRSTS_BITS,
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X38_ERRSTS_BITS);
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}
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static u64 x38_readq(const void __iomem *addr)
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{
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return readl(addr) | (((u64)readl(addr + 4)) << 32);
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}
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static void x38_get_and_clear_error_info(struct mem_ctl_info *mci,
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struct x38_error_info *info)
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{
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struct pci_dev *pdev;
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void __iomem *window = mci->pvt_info;
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pdev = to_pci_dev(mci->dev);
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/*
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* This is a mess because there is no atomic way to read all the
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* registers at once and the registers can transition from CE being
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* overwritten by UE.
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*/
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pci_read_config_word(pdev, X38_ERRSTS, &info->errsts);
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if (!(info->errsts & X38_ERRSTS_BITS))
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return;
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info->eccerrlog[0] = x38_readq(window + X38_C0ECCERRLOG);
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if (x38_channel_num == 2)
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info->eccerrlog[1] = x38_readq(window + X38_C1ECCERRLOG);
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pci_read_config_word(pdev, X38_ERRSTS, &info->errsts2);
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/*
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* If the error is the same for both reads then the first set
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* of reads is valid. If there is a change then there is a CE
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* with no info and the second set of reads is valid and
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* should be UE info.
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*/
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if ((info->errsts ^ info->errsts2) & X38_ERRSTS_BITS) {
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info->eccerrlog[0] = x38_readq(window + X38_C0ECCERRLOG);
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if (x38_channel_num == 2)
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info->eccerrlog[1] =
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x38_readq(window + X38_C1ECCERRLOG);
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}
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x38_clear_error_info(mci);
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}
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static void x38_process_error_info(struct mem_ctl_info *mci,
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struct x38_error_info *info)
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{
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int channel;
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u64 log;
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if (!(info->errsts & X38_ERRSTS_BITS))
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return;
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if ((info->errsts ^ info->errsts2) & X38_ERRSTS_BITS) {
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edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
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info->errsts = info->errsts2;
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}
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for (channel = 0; channel < x38_channel_num; channel++) {
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log = info->eccerrlog[channel];
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if (log & X38_ECCERRLOG_UE) {
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edac_mc_handle_ue(mci, 0, 0,
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eccerrlog_row(channel, log), "x38 UE");
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} else if (log & X38_ECCERRLOG_CE) {
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edac_mc_handle_ce(mci, 0, 0,
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eccerrlog_syndrome(log),
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eccerrlog_row(channel, log), 0, "x38 CE");
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}
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}
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}
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static void x38_check(struct mem_ctl_info *mci)
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{
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struct x38_error_info info;
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debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
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x38_get_and_clear_error_info(mci, &info);
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x38_process_error_info(mci, &info);
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}
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void __iomem *x38_map_mchbar(struct pci_dev *pdev)
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{
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union {
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u64 mchbar;
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struct {
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u32 mchbar_low;
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u32 mchbar_high;
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};
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} u;
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void __iomem *window;
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pci_read_config_dword(pdev, X38_MCHBAR_LOW, &u.mchbar_low);
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pci_write_config_dword(pdev, X38_MCHBAR_LOW, u.mchbar_low | 0x1);
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pci_read_config_dword(pdev, X38_MCHBAR_HIGH, &u.mchbar_high);
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u.mchbar &= X38_MCHBAR_MASK;
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if (u.mchbar != (resource_size_t)u.mchbar) {
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printk(KERN_ERR
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"x38: mmio space beyond accessible range (0x%llx)\n",
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(unsigned long long)u.mchbar);
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return NULL;
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}
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window = ioremap_nocache(u.mchbar, X38_MMR_WINDOW_SIZE);
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if (!window)
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printk(KERN_ERR "x38: cannot map mmio space at 0x%llx\n",
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(unsigned long long)u.mchbar);
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return window;
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}
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static void x38_get_drbs(void __iomem *window,
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u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL])
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{
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int i;
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for (i = 0; i < X38_RANKS_PER_CHANNEL; i++) {
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drbs[0][i] = readw(window + X38_C0DRB + 2*i) & X38_DRB_MASK;
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drbs[1][i] = readw(window + X38_C1DRB + 2*i) & X38_DRB_MASK;
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}
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}
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static bool x38_is_stacked(struct pci_dev *pdev,
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u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL])
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{
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u16 tom;
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pci_read_config_word(pdev, X38_TOM, &tom);
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tom &= X38_TOM_MASK;
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return drbs[X38_CHANNELS - 1][X38_RANKS_PER_CHANNEL - 1] == tom;
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}
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static unsigned long drb_to_nr_pages(
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u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL],
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bool stacked, int channel, int rank)
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{
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int n;
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n = drbs[channel][rank];
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if (rank > 0)
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n -= drbs[channel][rank - 1];
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if (stacked && (channel == 1) && drbs[channel][rank] ==
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drbs[channel][X38_RANKS_PER_CHANNEL - 1]) {
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n -= drbs[0][X38_RANKS_PER_CHANNEL - 1];
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}
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n <<= (X38_DRB_SHIFT - PAGE_SHIFT);
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return n;
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}
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static int x38_probe1(struct pci_dev *pdev, int dev_idx)
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{
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int rc;
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int i;
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struct mem_ctl_info *mci = NULL;
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unsigned long last_page;
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u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL];
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bool stacked;
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void __iomem *window;
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debugf0("MC: %s()\n", __func__);
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window = x38_map_mchbar(pdev);
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if (!window)
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return -ENODEV;
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x38_get_drbs(window, drbs);
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how_many_channel(pdev);
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/* FIXME: unconventional pvt_info usage */
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mci = edac_mc_alloc(0, X38_RANKS, x38_channel_num, 0);
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if (!mci)
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return -ENOMEM;
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debugf3("MC: %s(): init mci\n", __func__);
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mci->dev = &pdev->dev;
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mci->mtype_cap = MEM_FLAG_DDR2;
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mci->edac_ctl_cap = EDAC_FLAG_SECDED;
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mci->edac_cap = EDAC_FLAG_SECDED;
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mci->mod_name = EDAC_MOD_STR;
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mci->mod_ver = X38_REVISION;
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mci->ctl_name = x38_devs[dev_idx].ctl_name;
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mci->dev_name = pci_name(pdev);
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mci->edac_check = x38_check;
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mci->ctl_page_to_phys = NULL;
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mci->pvt_info = window;
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stacked = x38_is_stacked(pdev, drbs);
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/*
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* The dram rank boundary (DRB) reg values are boundary addresses
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* for each DRAM rank with a granularity of 64MB. DRB regs are
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* cumulative; the last one will contain the total memory
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* contained in all ranks.
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*/
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last_page = -1UL;
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for (i = 0; i < mci->nr_csrows; i++) {
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unsigned long nr_pages;
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struct csrow_info *csrow = &mci->csrows[i];
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nr_pages = drb_to_nr_pages(drbs, stacked,
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i / X38_RANKS_PER_CHANNEL,
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i % X38_RANKS_PER_CHANNEL);
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if (nr_pages == 0) {
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csrow->mtype = MEM_EMPTY;
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continue;
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}
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csrow->first_page = last_page + 1;
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last_page += nr_pages;
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csrow->last_page = last_page;
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csrow->nr_pages = nr_pages;
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csrow->grain = nr_pages << PAGE_SHIFT;
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csrow->mtype = MEM_DDR2;
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csrow->dtype = DEV_UNKNOWN;
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csrow->edac_mode = EDAC_UNKNOWN;
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}
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x38_clear_error_info(mci);
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rc = -ENODEV;
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if (edac_mc_add_mc(mci)) {
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debugf3("MC: %s(): failed edac_mc_add_mc()\n", __func__);
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goto fail;
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}
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/* get this far and it's successful */
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debugf3("MC: %s(): success\n", __func__);
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return 0;
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fail:
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iounmap(window);
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if (mci)
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edac_mc_free(mci);
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return rc;
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}
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static int __devinit x38_init_one(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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int rc;
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debugf0("MC: %s()\n", __func__);
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if (pci_enable_device(pdev) < 0)
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return -EIO;
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rc = x38_probe1(pdev, ent->driver_data);
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if (!mci_pdev)
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mci_pdev = pci_dev_get(pdev);
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return rc;
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}
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static void __devexit x38_remove_one(struct pci_dev *pdev)
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{
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struct mem_ctl_info *mci;
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debugf0("%s()\n", __func__);
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mci = edac_mc_del_mc(&pdev->dev);
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if (!mci)
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return;
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iounmap(mci->pvt_info);
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edac_mc_free(mci);
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}
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static const struct pci_device_id x38_pci_tbl[] __devinitdata = {
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|
{
|
|
PCI_VEND_DEV(INTEL, X38_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
|
|
X38},
|
|
{
|
|
0,
|
|
} /* 0 terminated list. */
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci, x38_pci_tbl);
|
|
|
|
static struct pci_driver x38_driver = {
|
|
.name = EDAC_MOD_STR,
|
|
.probe = x38_init_one,
|
|
.remove = __devexit_p(x38_remove_one),
|
|
.id_table = x38_pci_tbl,
|
|
};
|
|
|
|
static int __init x38_init(void)
|
|
{
|
|
int pci_rc;
|
|
|
|
debugf3("MC: %s()\n", __func__);
|
|
|
|
/* Ensure that the OPSTATE is set correctly for POLL or NMI */
|
|
opstate_init();
|
|
|
|
pci_rc = pci_register_driver(&x38_driver);
|
|
if (pci_rc < 0)
|
|
goto fail0;
|
|
|
|
if (!mci_pdev) {
|
|
x38_registered = 0;
|
|
mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
|
|
PCI_DEVICE_ID_INTEL_X38_HB, NULL);
|
|
if (!mci_pdev) {
|
|
debugf0("x38 pci_get_device fail\n");
|
|
pci_rc = -ENODEV;
|
|
goto fail1;
|
|
}
|
|
|
|
pci_rc = x38_init_one(mci_pdev, x38_pci_tbl);
|
|
if (pci_rc < 0) {
|
|
debugf0("x38 init fail\n");
|
|
pci_rc = -ENODEV;
|
|
goto fail1;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
fail1:
|
|
pci_unregister_driver(&x38_driver);
|
|
|
|
fail0:
|
|
if (mci_pdev)
|
|
pci_dev_put(mci_pdev);
|
|
|
|
return pci_rc;
|
|
}
|
|
|
|
static void __exit x38_exit(void)
|
|
{
|
|
debugf3("MC: %s()\n", __func__);
|
|
|
|
pci_unregister_driver(&x38_driver);
|
|
if (!x38_registered) {
|
|
x38_remove_one(mci_pdev);
|
|
pci_dev_put(mci_pdev);
|
|
}
|
|
}
|
|
|
|
module_init(x38_init);
|
|
module_exit(x38_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Cluster Computing, Inc. Hitoshi Mitake");
|
|
MODULE_DESCRIPTION("MC support for Intel X38 memory hub controllers");
|
|
|
|
module_param(edac_op_state, int, 0444);
|
|
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
|