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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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5a0e3ad6af
percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
796 lines
23 KiB
C
796 lines
23 KiB
C
/* gerdes_amd7930.c,v 0.99 2001/10/02
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*
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* gerdes_amd7930.c Amd 79C30A and 79C32A specific routines
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* (based on HiSax driver by Karsten Keil)
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*
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* Author Christoph Ersfeld <info@formula-n.de>
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* Formula-n Europe AG (www.formula-n.com)
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* previously Gerdes AG
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*
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*
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* This file is (c) under GNU PUBLIC LICENSE
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*
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*
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* Notes:
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* Version 0.99 is the first release of this driver and there are
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* certainly a few bugs.
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*
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* Please don't report any malfunction to me without sending
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* (compressed) debug-logs.
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* It would be nearly impossible to retrace it.
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*
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* Log D-channel-processing as follows:
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*
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* 1. Load hisax with card-specific parameters, this example ist for
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* Formula-n enter:now ISDN PCI and compatible
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* (f.e. Gerdes Power ISDN PCI)
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*
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* modprobe hisax type=41 protocol=2 id=gerdes
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*
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* if you chose an other value for id, you need to modify the
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* code below, too.
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*
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* 2. set debug-level
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*
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* hisaxctrl gerdes 1 0x3ff
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* hisaxctrl gerdes 11 0x4f
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* cat /dev/isdnctrl >> ~/log &
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*
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* Please take also a look into /var/log/messages if there is
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* anything importand concerning HISAX.
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*
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*
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* Credits:
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* Programming the driver for Formula-n enter:now ISDN PCI and
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* necessary this driver for the used Amd 7930 D-channel-controller
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* was spnsored by Formula-n Europe AG.
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* Thanks to Karsten Keil and Petr Novak, who gave me support in
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* Hisax-specific questions.
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* I want so say special thanks to Carl-Friedrich Braun, who had to
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* answer a lot of questions about generally ISDN and about handling
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* of the Amd-Chip.
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*
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*/
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#include "hisax.h"
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#include "isdnl1.h"
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#include "isac.h"
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#include "amd7930_fn.h"
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/gfp.h>
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static void Amd7930_new_ph(struct IsdnCardState *cs);
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static WORD initAMD[] = {
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0x0100,
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0x00A5, 3, 0x01, 0x40, 0x58, // LPR, LMR1, LMR2
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0x0086, 1, 0x0B, // DMR1 (D-Buffer TH-Interrupts on)
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0x0087, 1, 0xFF, // DMR2
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0x0092, 1, 0x03, // EFCR (extended mode d-channel-fifo on)
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0x0090, 4, 0xFE, 0xFF, 0x02, 0x0F, // FRAR4, SRAR4, DMR3, DMR4 (address recognition )
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0x0084, 2, 0x80, 0x00, // DRLR
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0x00C0, 1, 0x47, // PPCR1
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0x00C8, 1, 0x01, // PPCR2
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0x0102,
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0x0107,
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0x01A1, 1,
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0x0121, 1,
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0x0189, 2,
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0x0045, 4, 0x61, 0x72, 0x00, 0x00, // MCR1, MCR2, MCR3, MCR4
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0x0063, 2, 0x08, 0x08, // GX
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0x0064, 2, 0x08, 0x08, // GR
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0x0065, 2, 0x99, 0x00, // GER
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0x0066, 2, 0x7C, 0x8B, // STG
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0x0067, 2, 0x00, 0x00, // FTGR1, FTGR2
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0x0068, 2, 0x20, 0x20, // ATGR1, ATGR2
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0x0069, 1, 0x4F, // MMR1
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0x006A, 1, 0x00, // MMR2
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0x006C, 1, 0x40, // MMR3
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0x0021, 1, 0x02, // INIT
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0x00A3, 1, 0x40, // LMR1
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0xFFFF
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};
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static void /* macro wWordAMD */
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WriteWordAmd7930(struct IsdnCardState *cs, BYTE reg, WORD val)
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{
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wByteAMD(cs, 0x00, reg);
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wByteAMD(cs, 0x01, LOBYTE(val));
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wByteAMD(cs, 0x01, HIBYTE(val));
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}
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static WORD /* macro rWordAMD */
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ReadWordAmd7930(struct IsdnCardState *cs, BYTE reg)
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{
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WORD res;
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/* direct access register */
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if(reg < 8) {
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res = rByteAMD(cs, reg);
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res += 256*rByteAMD(cs, reg);
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}
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/* indirect access register */
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else {
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wByteAMD(cs, 0x00, reg);
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res = rByteAMD(cs, 0x01);
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res += 256*rByteAMD(cs, 0x01);
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}
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return (res);
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}
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static void
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Amd7930_ph_command(struct IsdnCardState *cs, u_char command, char *s)
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{
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if (cs->debug & L1_DEB_ISAC)
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debugl1(cs, "AMD7930: %s: ph_command 0x%02X", s, command);
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cs->dc.amd7930.lmr1 = command;
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wByteAMD(cs, 0xA3, command);
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}
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static BYTE i430States[] = {
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// to reset F3 F4 F5 F6 F7 F8 AR from
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0x01, 0x02, 0x00, 0x00, 0x00, 0x07, 0x05, 0x00, // init
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0x01, 0x02, 0x00, 0x00, 0x00, 0x07, 0x05, 0x00, // reset
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0x01, 0x02, 0x00, 0x00, 0x00, 0x09, 0x05, 0x04, // F3
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0x01, 0x02, 0x00, 0x00, 0x1B, 0x00, 0x00, 0x00, // F4
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0x01, 0x02, 0x00, 0x00, 0x1B, 0x00, 0x00, 0x00, // F5
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0x01, 0x03, 0x00, 0x00, 0x00, 0x06, 0x05, 0x00, // F6
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0x11, 0x13, 0x00, 0x00, 0x1B, 0x00, 0x15, 0x00, // F7
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0x01, 0x03, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, // F8
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0x01, 0x03, 0x00, 0x00, 0x00, 0x09, 0x00, 0x0A}; // AR
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/* Row init - reset F3 F4 F5 F6 F7 F8 AR */
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static BYTE stateHelper[] = { 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08 };
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static void
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Amd7930_get_state(struct IsdnCardState *cs) {
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BYTE lsr = rByteAMD(cs, 0xA1);
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cs->dc.amd7930.ph_state = (lsr & 0x7) + 2;
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Amd7930_new_ph(cs);
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}
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static void
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Amd7930_new_ph(struct IsdnCardState *cs)
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{
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u_char index = stateHelper[cs->dc.amd7930.old_state]*8 + stateHelper[cs->dc.amd7930.ph_state]-1;
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u_char message = i430States[index];
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if (cs->debug & L1_DEB_ISAC)
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debugl1(cs, "AMD7930: new_ph %d, old_ph %d, message %d, index %d",
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cs->dc.amd7930.ph_state, cs->dc.amd7930.old_state, message & 0x0f, index);
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cs->dc.amd7930.old_state = cs->dc.amd7930.ph_state;
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/* abort transmit if nessesary */
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if ((message & 0xf0) && (cs->tx_skb)) {
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wByteAMD(cs, 0x21, 0xC2);
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wByteAMD(cs, 0x21, 0x02);
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}
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switch (message & 0x0f) {
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case (1):
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l1_msg(cs, HW_RESET | INDICATION, NULL);
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Amd7930_get_state(cs);
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break;
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case (2): /* init, Card starts in F3 */
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l1_msg(cs, HW_DEACTIVATE | CONFIRM, NULL);
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break;
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case (3):
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l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
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break;
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case (4):
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l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
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Amd7930_ph_command(cs, 0x50, "HW_ENABLE REQUEST");
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break;
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case (5):
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l1_msg(cs, HW_RSYNC | INDICATION, NULL);
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break;
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case (6):
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l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
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break;
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case (7): /* init, Card starts in F7 */
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l1_msg(cs, HW_RSYNC | INDICATION, NULL);
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l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
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break;
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case (8):
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l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
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/* fall through */
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case (9):
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Amd7930_ph_command(cs, 0x40, "HW_ENABLE REQ cleared if set");
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l1_msg(cs, HW_RSYNC | INDICATION, NULL);
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l1_msg(cs, HW_INFO2 | INDICATION, NULL);
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l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
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break;
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case (10):
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Amd7930_ph_command(cs, 0x40, "T3 expired, HW_ENABLE REQ cleared");
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cs->dc.amd7930.old_state = 3;
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break;
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case (11):
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l1_msg(cs, HW_INFO2 | INDICATION, NULL);
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break;
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default:
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break;
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}
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}
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static void
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Amd7930_bh(struct work_struct *work)
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{
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struct IsdnCardState *cs =
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container_of(work, struct IsdnCardState, tqueue);
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struct PStack *stptr;
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if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {
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if (cs->debug)
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debugl1(cs, "Amd7930: bh, D-Channel Busy cleared");
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stptr = cs->stlist;
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while (stptr != NULL) {
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stptr->l1.l1l2(stptr, PH_PAUSE | CONFIRM, NULL);
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stptr = stptr->next;
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}
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}
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if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
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if (cs->debug & L1_DEB_ISAC)
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debugl1(cs, "AMD7930: bh, D_L1STATECHANGE");
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Amd7930_new_ph(cs);
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}
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if (test_and_clear_bit(D_RCVBUFREADY, &cs->event)) {
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if (cs->debug & L1_DEB_ISAC)
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debugl1(cs, "AMD7930: bh, D_RCVBUFREADY");
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DChannel_proc_rcv(cs);
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}
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if (test_and_clear_bit(D_XMTBUFREADY, &cs->event)) {
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if (cs->debug & L1_DEB_ISAC)
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debugl1(cs, "AMD7930: bh, D_XMTBUFREADY");
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DChannel_proc_xmt(cs);
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}
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}
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static void
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Amd7930_empty_Dfifo(struct IsdnCardState *cs, int flag)
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{
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BYTE stat, der;
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BYTE *ptr;
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struct sk_buff *skb;
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if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
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debugl1(cs, "Amd7930: empty_Dfifo");
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ptr = cs->rcvbuf + cs->rcvidx;
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/* AMD interrupts off */
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AmdIrqOff(cs);
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/* read D-Channel-Fifo*/
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stat = rByteAMD(cs, 0x07); // DSR2
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/* while Data in Fifo ... */
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while ( (stat & 2) && ((ptr-cs->rcvbuf) < MAX_DFRAME_LEN_L1) ) {
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*ptr = rByteAMD(cs, 0x04); // DCRB
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ptr++;
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stat = rByteAMD(cs, 0x07); // DSR2
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cs->rcvidx = ptr - cs->rcvbuf;
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/* Paket ready? */
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if (stat & 1) {
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der = rWordAMD(cs, 0x03);
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/* no errors, packet ok */
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if(!der && !flag) {
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rWordAMD(cs, 0x89); // clear DRCR
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if ((cs->rcvidx) > 0) {
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if (!(skb = alloc_skb(cs->rcvidx, GFP_ATOMIC)))
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printk(KERN_WARNING "HiSax: Amd7930: empty_Dfifo, D receive out of memory!\n");
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else {
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/* Debugging */
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if (cs->debug & L1_DEB_ISAC_FIFO) {
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char *t = cs->dlog;
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t += sprintf(t, "Amd7930: empty_Dfifo cnt: %d |", cs->rcvidx);
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QuickHex(t, cs->rcvbuf, cs->rcvidx);
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debugl1(cs, cs->dlog);
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}
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/* moves received data in sk-buffer */
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memcpy(skb_put(skb, cs->rcvidx), cs->rcvbuf, cs->rcvidx);
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skb_queue_tail(&cs->rq, skb);
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}
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}
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}
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/* throw damaged packets away, reset receive-buffer, indicate RX */
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ptr = cs->rcvbuf;
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cs->rcvidx = 0;
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schedule_event(cs, D_RCVBUFREADY);
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}
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}
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/* Packet to long, overflow */
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if(cs->rcvidx >= MAX_DFRAME_LEN_L1) {
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "AMD7930: empty_Dfifo L2-Framelength overrun");
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cs->rcvidx = 0;
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return;
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}
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/* AMD interrupts on */
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AmdIrqOn(cs);
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}
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static void
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Amd7930_fill_Dfifo(struct IsdnCardState *cs)
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{
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WORD dtcrr, dtcrw, len, count;
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BYTE txstat, dmr3;
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BYTE *ptr, *deb_ptr;
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if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
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debugl1(cs, "Amd7930: fill_Dfifo");
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if ((!cs->tx_skb) || (cs->tx_skb->len <= 0))
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return;
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dtcrw = 0;
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if(!cs->dc.amd7930.tx_xmtlen)
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/* new Frame */
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len = dtcrw = cs->tx_skb->len;
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/* continue frame */
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else len = cs->dc.amd7930.tx_xmtlen;
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/* AMD interrupts off */
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AmdIrqOff(cs);
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deb_ptr = ptr = cs->tx_skb->data;
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/* while free place in tx-fifo available and data in sk-buffer */
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txstat = 0x10;
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while((txstat & 0x10) && (cs->tx_cnt < len)) {
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wByteAMD(cs, 0x04, *ptr);
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ptr++;
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cs->tx_cnt++;
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txstat= rByteAMD(cs, 0x07);
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}
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count = ptr - cs->tx_skb->data;
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skb_pull(cs->tx_skb, count);
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dtcrr = rWordAMD(cs, 0x85); // DTCR
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dmr3 = rByteAMD(cs, 0x8E);
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if (cs->debug & L1_DEB_ISAC) {
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debugl1(cs, "Amd7930: fill_Dfifo, DMR3: 0x%02X, DTCR read: 0x%04X write: 0x%02X 0x%02X", dmr3, dtcrr, LOBYTE(dtcrw), HIBYTE(dtcrw));
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}
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/* writeing of dtcrw starts transmit */
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if(!cs->dc.amd7930.tx_xmtlen) {
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wWordAMD(cs, 0x85, dtcrw);
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cs->dc.amd7930.tx_xmtlen = dtcrw;
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}
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if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
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debugl1(cs, "Amd7930: fill_Dfifo dbusytimer running");
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del_timer(&cs->dbusytimer);
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}
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init_timer(&cs->dbusytimer);
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cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ) / 1000);
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add_timer(&cs->dbusytimer);
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if (cs->debug & L1_DEB_ISAC_FIFO) {
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char *t = cs->dlog;
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|
|
|
t += sprintf(t, "Amd7930: fill_Dfifo cnt: %d |", count);
|
|
QuickHex(t, deb_ptr, count);
|
|
debugl1(cs, cs->dlog);
|
|
}
|
|
/* AMD interrupts on */
|
|
AmdIrqOn(cs);
|
|
}
|
|
|
|
|
|
void Amd7930_interrupt(struct IsdnCardState *cs, BYTE irflags)
|
|
{
|
|
BYTE dsr1, dsr2, lsr;
|
|
WORD der;
|
|
|
|
while (irflags)
|
|
{
|
|
|
|
dsr1 = rByteAMD(cs, 0x02);
|
|
der = rWordAMD(cs, 0x03);
|
|
dsr2 = rByteAMD(cs, 0x07);
|
|
lsr = rByteAMD(cs, 0xA1);
|
|
|
|
if (cs->debug & L1_DEB_ISAC)
|
|
debugl1(cs, "Amd7930: interrupt: flags: 0x%02X, DSR1: 0x%02X, DSR2: 0x%02X, LSR: 0x%02X, DER=0x%04X", irflags, dsr1, dsr2, lsr, der);
|
|
|
|
/* D error -> read DER and DSR2 bit 2 */
|
|
if (der || (dsr2 & 4)) {
|
|
|
|
if (cs->debug & L1_DEB_WARN)
|
|
debugl1(cs, "Amd7930: interrupt: D error DER=0x%04X", der);
|
|
|
|
/* RX, TX abort if collision detected */
|
|
if (der & 2) {
|
|
wByteAMD(cs, 0x21, 0xC2);
|
|
wByteAMD(cs, 0x21, 0x02);
|
|
if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
|
|
del_timer(&cs->dbusytimer);
|
|
if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
|
|
schedule_event(cs, D_CLEARBUSY);
|
|
/* restart frame */
|
|
if (cs->tx_skb) {
|
|
skb_push(cs->tx_skb, cs->tx_cnt);
|
|
cs->tx_cnt = 0;
|
|
cs->dc.amd7930.tx_xmtlen = 0;
|
|
Amd7930_fill_Dfifo(cs);
|
|
} else {
|
|
printk(KERN_WARNING "HiSax: Amd7930 D-Collision, no skb\n");
|
|
debugl1(cs, "Amd7930: interrupt: D-Collision, no skb");
|
|
}
|
|
}
|
|
/* remove damaged data from fifo */
|
|
Amd7930_empty_Dfifo(cs, 1);
|
|
|
|
if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
|
|
del_timer(&cs->dbusytimer);
|
|
if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
|
|
schedule_event(cs, D_CLEARBUSY);
|
|
/* restart TX-Frame */
|
|
if (cs->tx_skb) {
|
|
skb_push(cs->tx_skb, cs->tx_cnt);
|
|
cs->tx_cnt = 0;
|
|
cs->dc.amd7930.tx_xmtlen = 0;
|
|
Amd7930_fill_Dfifo(cs);
|
|
}
|
|
}
|
|
|
|
/* D TX FIFO empty -> fill */
|
|
if (irflags & 1) {
|
|
if (cs->debug & L1_DEB_ISAC)
|
|
debugl1(cs, "Amd7930: interrupt: clear Timer and fill D-TX-FIFO if data");
|
|
|
|
/* AMD interrupts off */
|
|
AmdIrqOff(cs);
|
|
|
|
if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
|
|
del_timer(&cs->dbusytimer);
|
|
if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
|
|
schedule_event(cs, D_CLEARBUSY);
|
|
if (cs->tx_skb) {
|
|
if (cs->tx_skb->len)
|
|
Amd7930_fill_Dfifo(cs);
|
|
}
|
|
/* AMD interrupts on */
|
|
AmdIrqOn(cs);
|
|
}
|
|
|
|
|
|
/* D RX FIFO full or tiny packet in Fifo -> empty */
|
|
if ((irflags & 2) || (dsr1 & 2)) {
|
|
if (cs->debug & L1_DEB_ISAC)
|
|
debugl1(cs, "Amd7930: interrupt: empty D-FIFO");
|
|
Amd7930_empty_Dfifo(cs, 0);
|
|
}
|
|
|
|
|
|
/* D-Frame transmit complete */
|
|
if (dsr1 & 64) {
|
|
if (cs->debug & L1_DEB_ISAC) {
|
|
debugl1(cs, "Amd7930: interrupt: transmit packet ready");
|
|
}
|
|
/* AMD interrupts off */
|
|
AmdIrqOff(cs);
|
|
|
|
if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
|
|
del_timer(&cs->dbusytimer);
|
|
if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
|
|
schedule_event(cs, D_CLEARBUSY);
|
|
|
|
if (cs->tx_skb) {
|
|
if (cs->debug & L1_DEB_ISAC)
|
|
debugl1(cs, "Amd7930: interrupt: TX-Packet ready, freeing skb");
|
|
dev_kfree_skb_irq(cs->tx_skb);
|
|
cs->tx_cnt = 0;
|
|
cs->dc.amd7930.tx_xmtlen=0;
|
|
cs->tx_skb = NULL;
|
|
}
|
|
if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
|
|
if (cs->debug & L1_DEB_ISAC)
|
|
debugl1(cs, "Amd7930: interrupt: TX-Packet ready, next packet dequeued");
|
|
cs->tx_cnt = 0;
|
|
cs->dc.amd7930.tx_xmtlen=0;
|
|
Amd7930_fill_Dfifo(cs);
|
|
}
|
|
else
|
|
schedule_event(cs, D_XMTBUFREADY);
|
|
/* AMD interrupts on */
|
|
AmdIrqOn(cs);
|
|
}
|
|
|
|
/* LIU status interrupt -> read LSR, check statechanges */
|
|
if (lsr & 0x38) {
|
|
/* AMD interrupts off */
|
|
AmdIrqOff(cs);
|
|
|
|
if (cs->debug & L1_DEB_ISAC)
|
|
debugl1(cs, "Amd: interrupt: LSR=0x%02X, LIU is in state %d", lsr, ((lsr & 0x7) +2));
|
|
|
|
cs->dc.amd7930.ph_state = (lsr & 0x7) + 2;
|
|
|
|
schedule_event(cs, D_L1STATECHANGE);
|
|
/* AMD interrupts on */
|
|
AmdIrqOn(cs);
|
|
}
|
|
|
|
/* reads Interrupt-Register again. If there is a new interrupt-flag: restart handler */
|
|
irflags = rByteAMD(cs, 0x00);
|
|
}
|
|
|
|
}
|
|
|
|
static void
|
|
Amd7930_l1hw(struct PStack *st, int pr, void *arg)
|
|
{
|
|
struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
|
|
struct sk_buff *skb = arg;
|
|
u_long flags;
|
|
|
|
if (cs->debug & L1_DEB_ISAC)
|
|
debugl1(cs, "Amd7930: l1hw called, pr: 0x%04X", pr);
|
|
|
|
switch (pr) {
|
|
case (PH_DATA | REQUEST):
|
|
if (cs->debug & DEB_DLOG_HEX)
|
|
LogFrame(cs, skb->data, skb->len);
|
|
if (cs->debug & DEB_DLOG_VERBOSE)
|
|
dlogframe(cs, skb, 0);
|
|
spin_lock_irqsave(&cs->lock, flags);
|
|
if (cs->tx_skb) {
|
|
skb_queue_tail(&cs->sq, skb);
|
|
#ifdef L2FRAME_DEBUG /* psa */
|
|
if (cs->debug & L1_DEB_LAPD)
|
|
Logl2Frame(cs, skb, "Amd7930: l1hw: PH_DATA Queued", 0);
|
|
#endif
|
|
} else {
|
|
cs->tx_skb = skb;
|
|
cs->tx_cnt = 0;
|
|
cs->dc.amd7930.tx_xmtlen=0;
|
|
#ifdef L2FRAME_DEBUG /* psa */
|
|
if (cs->debug & L1_DEB_LAPD)
|
|
Logl2Frame(cs, skb, "Amd7930: l1hw: PH_DATA", 0);
|
|
#endif
|
|
Amd7930_fill_Dfifo(cs);
|
|
}
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
break;
|
|
case (PH_PULL | INDICATION):
|
|
spin_lock_irqsave(&cs->lock, flags);
|
|
if (cs->tx_skb) {
|
|
if (cs->debug & L1_DEB_WARN)
|
|
debugl1(cs, "Amd7930: l1hw: l2l1 tx_skb exist this shouldn't happen");
|
|
skb_queue_tail(&cs->sq, skb);
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
break;
|
|
}
|
|
if (cs->debug & DEB_DLOG_HEX)
|
|
LogFrame(cs, skb->data, skb->len);
|
|
if (cs->debug & DEB_DLOG_VERBOSE)
|
|
dlogframe(cs, skb, 0);
|
|
cs->tx_skb = skb;
|
|
cs->tx_cnt = 0;
|
|
cs->dc.amd7930.tx_xmtlen=0;
|
|
#ifdef L2FRAME_DEBUG /* psa */
|
|
if (cs->debug & L1_DEB_LAPD)
|
|
Logl2Frame(cs, skb, "Amd7930: l1hw: PH_DATA_PULLED", 0);
|
|
#endif
|
|
Amd7930_fill_Dfifo(cs);
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
break;
|
|
case (PH_PULL | REQUEST):
|
|
#ifdef L2FRAME_DEBUG /* psa */
|
|
if (cs->debug & L1_DEB_LAPD)
|
|
debugl1(cs, "Amd7930: l1hw: -> PH_REQUEST_PULL, skb: %s", (cs->tx_skb)? "yes":"no");
|
|
#endif
|
|
if (!cs->tx_skb) {
|
|
test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
|
|
st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
|
|
} else
|
|
test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
|
|
break;
|
|
case (HW_RESET | REQUEST):
|
|
spin_lock_irqsave(&cs->lock, flags);
|
|
if ((cs->dc.amd7930.ph_state == 8)) {
|
|
/* b-channels off, PH-AR cleared
|
|
* change to F3 */
|
|
Amd7930_ph_command(cs, 0x20, "HW_RESET REQEST"); //LMR1 bit 5
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
} else {
|
|
Amd7930_ph_command(cs, 0x40, "HW_RESET REQUEST");
|
|
cs->dc.amd7930.ph_state = 2;
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
Amd7930_new_ph(cs);
|
|
}
|
|
break;
|
|
case (HW_ENABLE | REQUEST):
|
|
cs->dc.amd7930.ph_state = 9;
|
|
Amd7930_new_ph(cs);
|
|
break;
|
|
case (HW_INFO3 | REQUEST):
|
|
// automatic
|
|
break;
|
|
case (HW_TESTLOOP | REQUEST):
|
|
/* not implemented yet */
|
|
break;
|
|
case (HW_DEACTIVATE | RESPONSE):
|
|
skb_queue_purge(&cs->rq);
|
|
skb_queue_purge(&cs->sq);
|
|
if (cs->tx_skb) {
|
|
dev_kfree_skb(cs->tx_skb);
|
|
cs->tx_skb = NULL;
|
|
}
|
|
if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
|
|
del_timer(&cs->dbusytimer);
|
|
if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
|
|
schedule_event(cs, D_CLEARBUSY);
|
|
break;
|
|
default:
|
|
if (cs->debug & L1_DEB_WARN)
|
|
debugl1(cs, "Amd7930: l1hw: unknown %04x", pr);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void
|
|
setstack_Amd7930(struct PStack *st, struct IsdnCardState *cs)
|
|
{
|
|
|
|
if (cs->debug & L1_DEB_ISAC)
|
|
debugl1(cs, "Amd7930: setstack called");
|
|
|
|
st->l1.l1hw = Amd7930_l1hw;
|
|
}
|
|
|
|
|
|
static void
|
|
DC_Close_Amd7930(struct IsdnCardState *cs) {
|
|
if (cs->debug & L1_DEB_ISAC)
|
|
debugl1(cs, "Amd7930: DC_Close called");
|
|
}
|
|
|
|
|
|
static void
|
|
dbusy_timer_handler(struct IsdnCardState *cs)
|
|
{
|
|
u_long flags;
|
|
struct PStack *stptr;
|
|
WORD dtcr, der;
|
|
BYTE dsr1, dsr2;
|
|
|
|
|
|
if (cs->debug & L1_DEB_ISAC)
|
|
debugl1(cs, "Amd7930: dbusy_timer expired!");
|
|
|
|
if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
|
|
spin_lock_irqsave(&cs->lock, flags);
|
|
/* D Transmit Byte Count Register:
|
|
* Counts down packet's number of Bytes, 0 if packet ready */
|
|
dtcr = rWordAMD(cs, 0x85);
|
|
dsr1 = rByteAMD(cs, 0x02);
|
|
dsr2 = rByteAMD(cs, 0x07);
|
|
der = rWordAMD(cs, 0x03);
|
|
|
|
if (cs->debug & L1_DEB_ISAC)
|
|
debugl1(cs, "Amd7930: dbusy_timer_handler: DSR1=0x%02X, DSR2=0x%02X, DER=0x%04X, cs->tx_skb->len=%u, tx_stat=%u, dtcr=%u, cs->tx_cnt=%u", dsr1, dsr2, der, cs->tx_skb->len, cs->dc.amd7930.tx_xmtlen, dtcr, cs->tx_cnt);
|
|
|
|
if ((cs->dc.amd7930.tx_xmtlen - dtcr) < cs->tx_cnt) { /* D-Channel Busy */
|
|
test_and_set_bit(FLG_L1_DBUSY, &cs->HW_Flags);
|
|
stptr = cs->stlist;
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
while (stptr != NULL) {
|
|
stptr->l1.l1l2(stptr, PH_PAUSE | INDICATION, NULL);
|
|
stptr = stptr->next;
|
|
}
|
|
|
|
} else {
|
|
/* discard frame; reset transceiver */
|
|
test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags);
|
|
if (cs->tx_skb) {
|
|
dev_kfree_skb_any(cs->tx_skb);
|
|
cs->tx_cnt = 0;
|
|
cs->tx_skb = NULL;
|
|
cs->dc.amd7930.tx_xmtlen = 0;
|
|
} else {
|
|
printk(KERN_WARNING "HiSax: Amd7930: D-Channel Busy no skb\n");
|
|
debugl1(cs, "Amd7930: D-Channel Busy no skb");
|
|
|
|
}
|
|
/* Transmitter reset, abort transmit */
|
|
wByteAMD(cs, 0x21, 0x82);
|
|
wByteAMD(cs, 0x21, 0x02);
|
|
spin_unlock_irqrestore(&cs->lock, flags);
|
|
cs->irq_func(cs->irq, cs);
|
|
|
|
if (cs->debug & L1_DEB_ISAC)
|
|
debugl1(cs, "Amd7930: dbusy_timer_handler: Transmitter reset");
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
|
|
void Amd7930_init(struct IsdnCardState *cs)
|
|
{
|
|
WORD *ptr;
|
|
BYTE cmd, cnt;
|
|
|
|
if (cs->debug & L1_DEB_ISAC)
|
|
debugl1(cs, "Amd7930: initamd called");
|
|
|
|
cs->dc.amd7930.tx_xmtlen = 0;
|
|
cs->dc.amd7930.old_state = 0;
|
|
cs->dc.amd7930.lmr1 = 0x40;
|
|
cs->dc.amd7930.ph_command = Amd7930_ph_command;
|
|
cs->setstack_d = setstack_Amd7930;
|
|
cs->DC_Close = DC_Close_Amd7930;
|
|
|
|
/* AMD Initialisation */
|
|
for (ptr = initAMD; *ptr != 0xFFFF; ) {
|
|
cmd = LOBYTE(*ptr);
|
|
|
|
/* read */
|
|
if (*ptr++ >= 0x100) {
|
|
if (cmd < 8)
|
|
/* reset register */
|
|
rByteAMD(cs, cmd);
|
|
else {
|
|
wByteAMD(cs, 0x00, cmd);
|
|
for (cnt = *ptr++; cnt > 0; cnt--)
|
|
rByteAMD(cs, 0x01);
|
|
}
|
|
}
|
|
/* write */
|
|
else if (cmd < 8)
|
|
wByteAMD(cs, cmd, LOBYTE(*ptr++));
|
|
|
|
else {
|
|
wByteAMD(cs, 0x00, cmd);
|
|
for (cnt = *ptr++; cnt > 0; cnt--)
|
|
wByteAMD(cs, 0x01, LOBYTE(*ptr++));
|
|
}
|
|
}
|
|
}
|
|
|
|
void __devinit
|
|
setup_Amd7930(struct IsdnCardState *cs)
|
|
{
|
|
INIT_WORK(&cs->tqueue, Amd7930_bh);
|
|
cs->dbusytimer.function = (void *) dbusy_timer_handler;
|
|
cs->dbusytimer.data = (long) cs;
|
|
init_timer(&cs->dbusytimer);
|
|
}
|