mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-15 23:25:07 +00:00
5a229c2a59
Add the necessary DT node to probe the rng driver on msm8960-cdp platform. Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com> Tested-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
129 lines
2.6 KiB
Text
129 lines
2.6 KiB
Text
/dts-v1/;
|
|
|
|
/include/ "skeleton.dtsi"
|
|
|
|
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
|
|
|
|
/ {
|
|
model = "Qualcomm MSM8960";
|
|
compatible = "qcom,msm8960";
|
|
interrupt-parent = <&intc>;
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <1 14 0x304>;
|
|
compatible = "qcom,krait";
|
|
enable-method = "qcom,kpss-acc-v1";
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
reg = <0>;
|
|
next-level-cache = <&L2>;
|
|
qcom,acc = <&acc0>;
|
|
qcom,saw = <&saw0>;
|
|
};
|
|
|
|
cpu@1 {
|
|
device_type = "cpu";
|
|
reg = <1>;
|
|
next-level-cache = <&L2>;
|
|
qcom,acc = <&acc1>;
|
|
qcom,saw = <&saw1>;
|
|
};
|
|
|
|
L2: l2-cache {
|
|
compatible = "cache";
|
|
cache-level = <2>;
|
|
interrupts = <0 2 0x4>;
|
|
};
|
|
};
|
|
|
|
intc: interrupt-controller@2000000 {
|
|
compatible = "qcom,msm-qgic2";
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
reg = < 0x02000000 0x1000 >,
|
|
< 0x02002000 0x1000 >;
|
|
};
|
|
|
|
timer@200a000 {
|
|
compatible = "qcom,kpss-timer", "qcom,msm-timer";
|
|
interrupts = <1 1 0x301>,
|
|
<1 2 0x301>,
|
|
<1 3 0x301>;
|
|
reg = <0x0200a000 0x100>;
|
|
clock-frequency = <27000000>,
|
|
<32768>;
|
|
cpu-offset = <0x80000>;
|
|
};
|
|
|
|
msmgpio: gpio@800000 {
|
|
compatible = "qcom,msm-gpio";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
ngpio = <150>;
|
|
interrupts = <0 16 0x4>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x800000 0x4000>;
|
|
};
|
|
|
|
gcc: clock-controller@900000 {
|
|
compatible = "qcom,gcc-msm8960";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
reg = <0x900000 0x4000>;
|
|
};
|
|
|
|
clock-controller@4000000 {
|
|
compatible = "qcom,mmcc-msm8960";
|
|
reg = <0x4000000 0x1000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
acc0: clock-controller@2088000 {
|
|
compatible = "qcom,kpss-acc-v1";
|
|
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
|
|
};
|
|
|
|
acc1: clock-controller@2098000 {
|
|
compatible = "qcom,kpss-acc-v1";
|
|
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
|
|
};
|
|
|
|
saw0: regulator@2089000 {
|
|
compatible = "qcom,saw2";
|
|
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
|
|
regulator;
|
|
};
|
|
|
|
saw1: regulator@2099000 {
|
|
compatible = "qcom,saw2";
|
|
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
|
|
regulator;
|
|
};
|
|
|
|
serial@16440000 {
|
|
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
|
reg = <0x16440000 0x1000>,
|
|
<0x16400000 0x1000>;
|
|
interrupts = <0 154 0x0>;
|
|
clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
};
|
|
|
|
qcom,ssbi@500000 {
|
|
compatible = "qcom,ssbi";
|
|
reg = <0x500000 0x1000>;
|
|
qcom,controller-type = "pmic-arbiter";
|
|
};
|
|
|
|
rng@1a500000 {
|
|
compatible = "qcom,prng";
|
|
reg = <0x1a500000 0x200>;
|
|
clocks = <&gcc PRNG_CLK>;
|
|
clock-names = "core";
|
|
};
|
|
};
|