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5a2b2e1341
Currently, xvcu_pll_set_rate configures the PLL to a clock rate that is pre-calculated when probing the driver. To still make the clock framework aware of the PLL and to allow to configure other clocks based on the PLL rate, register the PLL as a fixed rate clock. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210121071659.1226489-8-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
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amlogic | ||
aspeed | ||
atmel | ||
bcm | ||
dove | ||
fsl | ||
gemini | ||
imx | ||
ixp4xx | ||
kendryte | ||
lantiq | ||
litex | ||
mediatek | ||
qcom | ||
renesas | ||
rockchip | ||
samsung | ||
sifive | ||
sunxi | ||
tegra | ||
ti | ||
ux500 | ||
versatile | ||
xilinx | ||
zte | ||
Kconfig | ||
Makefile |