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efdf72ad5c
The frequency memory bus on Tegra can be adjusted without disabling accesses to memory by updating the memory configuration registers from a per-board table, and then changing the clock frequency. The clock controller and memory controller have an interlock that prevents the new memory registers from taking effect until the clock frequency change. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
178 lines
4.1 KiB
C
178 lines
4.1 KiB
C
/*
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* Copyright (C) 2011 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@android.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <mach/iomap.h>
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#include "tegra2_emc.h"
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#ifdef CONFIG_TEGRA_EMC_SCALING_ENABLE
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static bool emc_enable = true;
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#else
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static bool emc_enable;
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#endif
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module_param(emc_enable, bool, 0644);
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static void __iomem *emc = IO_ADDRESS(TEGRA_EMC_BASE);
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static const struct tegra_emc_table *tegra_emc_table;
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static int tegra_emc_table_size;
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static inline void emc_writel(u32 val, unsigned long addr)
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{
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writel(val, emc + addr);
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}
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static inline u32 emc_readl(unsigned long addr)
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{
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return readl(emc + addr);
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}
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static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = {
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0x2c, /* RC */
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0x30, /* RFC */
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0x34, /* RAS */
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0x38, /* RP */
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0x3c, /* R2W */
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0x40, /* W2R */
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0x44, /* R2P */
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0x48, /* W2P */
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0x4c, /* RD_RCD */
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0x50, /* WR_RCD */
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0x54, /* RRD */
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0x58, /* REXT */
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0x5c, /* WDV */
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0x60, /* QUSE */
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0x64, /* QRST */
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0x68, /* QSAFE */
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0x6c, /* RDV */
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0x70, /* REFRESH */
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0x74, /* BURST_REFRESH_NUM */
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0x78, /* PDEX2WR */
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0x7c, /* PDEX2RD */
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0x80, /* PCHG2PDEN */
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0x84, /* ACT2PDEN */
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0x88, /* AR2PDEN */
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0x8c, /* RW2PDEN */
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0x90, /* TXSR */
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0x94, /* TCKE */
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0x98, /* TFAW */
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0x9c, /* TRPAB */
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0xa0, /* TCLKSTABLE */
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0xa4, /* TCLKSTOP */
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0xa8, /* TREFBW */
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0xac, /* QUSE_EXTRA */
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0x114, /* FBIO_CFG6 */
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0xb0, /* ODT_WRITE */
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0xb4, /* ODT_READ */
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0x104, /* FBIO_CFG5 */
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0x2bc, /* CFG_DIG_DLL */
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0x2c0, /* DLL_XFORM_DQS */
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0x2c4, /* DLL_XFORM_QUSE */
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0x2e0, /* ZCAL_REF_CNT */
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0x2e4, /* ZCAL_WAIT_CNT */
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0x2a8, /* AUTO_CAL_INTERVAL */
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0x2d0, /* CFG_CLKTRIM_0 */
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0x2d4, /* CFG_CLKTRIM_1 */
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0x2d8, /* CFG_CLKTRIM_2 */
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};
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/* Select the closest EMC rate that is higher than the requested rate */
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long tegra_emc_round_rate(unsigned long rate)
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{
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int i;
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int best = -1;
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unsigned long distance = ULONG_MAX;
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if (!tegra_emc_table)
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return -EINVAL;
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if (!emc_enable)
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return -EINVAL;
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pr_debug("%s: %lu\n", __func__, rate);
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/*
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* The EMC clock rate is twice the bus rate, and the bus rate is
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* measured in kHz
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*/
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rate = rate / 2 / 1000;
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for (i = 0; i < tegra_emc_table_size; i++) {
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if (tegra_emc_table[i].rate >= rate &&
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(tegra_emc_table[i].rate - rate) < distance) {
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distance = tegra_emc_table[i].rate - rate;
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best = i;
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}
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}
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if (best < 0)
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return -EINVAL;
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pr_debug("%s: using %lu\n", __func__, tegra_emc_table[best].rate);
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return tegra_emc_table[best].rate * 2 * 1000;
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}
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/*
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* The EMC registers have shadow registers. When the EMC clock is updated
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* in the clock controller, the shadow registers are copied to the active
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* registers, allowing glitchless memory bus frequency changes.
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* This function updates the shadow registers for a new clock frequency,
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* and relies on the clock lock on the emc clock to avoid races between
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* multiple frequency changes
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*/
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int tegra_emc_set_rate(unsigned long rate)
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{
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int i;
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int j;
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if (!tegra_emc_table)
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return -EINVAL;
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/*
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* The EMC clock rate is twice the bus rate, and the bus rate is
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* measured in kHz
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*/
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rate = rate / 2 / 1000;
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for (i = 0; i < tegra_emc_table_size; i++)
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if (tegra_emc_table[i].rate == rate)
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break;
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if (i >= tegra_emc_table_size)
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return -EINVAL;
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pr_debug("%s: setting to %lu\n", __func__, rate);
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for (j = 0; j < TEGRA_EMC_NUM_REGS; j++)
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emc_writel(tegra_emc_table[i].regs[j], emc_reg_addr[j]);
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emc_readl(tegra_emc_table[i].regs[TEGRA_EMC_NUM_REGS - 1]);
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return 0;
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}
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void tegra_init_emc(const struct tegra_emc_table *table, int table_size)
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{
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tegra_emc_table = table;
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tegra_emc_table_size = table_size;
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}
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