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776b4a1cf3
The ZA array can be read and written with the NT_ARM_ZA. Similarly to our interface for the SVE vector registers the regset consists of a header with information on the current vector length followed by an optional register data payload, represented as for signals as a series of horizontal vectors from 0 to VL/8 in the endianness independent format used for vectors. On get if ZA is enabled then register data will be provided, otherwise it will be omitted. On set if register data is provided then ZA is enabled and initialized using the provided data, otherwise it is disabled. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20220419112247.711548-22-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
329 lines
9.5 KiB
C
329 lines
9.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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* Based on arch/arm/include/asm/ptrace.h
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*
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* Copyright (C) 1996-2003 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _UAPI__ASM_PTRACE_H
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#define _UAPI__ASM_PTRACE_H
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#include <linux/types.h>
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#include <asm/hwcap.h>
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#include <asm/sve_context.h>
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/*
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* PSR bits
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*/
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#define PSR_MODE_EL0t 0x00000000
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#define PSR_MODE_EL1t 0x00000004
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#define PSR_MODE_EL1h 0x00000005
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#define PSR_MODE_EL2t 0x00000008
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#define PSR_MODE_EL2h 0x00000009
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#define PSR_MODE_EL3t 0x0000000c
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#define PSR_MODE_EL3h 0x0000000d
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#define PSR_MODE_MASK 0x0000000f
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/* AArch32 CPSR bits */
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#define PSR_MODE32_BIT 0x00000010
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/* AArch64 SPSR bits */
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#define PSR_F_BIT 0x00000040
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#define PSR_I_BIT 0x00000080
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#define PSR_A_BIT 0x00000100
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#define PSR_D_BIT 0x00000200
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#define PSR_BTYPE_MASK 0x00000c00
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#define PSR_SSBS_BIT 0x00001000
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#define PSR_PAN_BIT 0x00400000
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#define PSR_UAO_BIT 0x00800000
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#define PSR_DIT_BIT 0x01000000
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#define PSR_TCO_BIT 0x02000000
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#define PSR_V_BIT 0x10000000
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#define PSR_C_BIT 0x20000000
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#define PSR_Z_BIT 0x40000000
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#define PSR_N_BIT 0x80000000
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#define PSR_BTYPE_SHIFT 10
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/*
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* Groups of PSR bits
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*/
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#define PSR_f 0xff000000 /* Flags */
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#define PSR_s 0x00ff0000 /* Status */
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#define PSR_x 0x0000ff00 /* Extension */
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#define PSR_c 0x000000ff /* Control */
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/* Convenience names for the values of PSTATE.BTYPE */
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#define PSR_BTYPE_NONE (0b00 << PSR_BTYPE_SHIFT)
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#define PSR_BTYPE_JC (0b01 << PSR_BTYPE_SHIFT)
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#define PSR_BTYPE_C (0b10 << PSR_BTYPE_SHIFT)
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#define PSR_BTYPE_J (0b11 << PSR_BTYPE_SHIFT)
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/* syscall emulation path in ptrace */
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#define PTRACE_SYSEMU 31
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#define PTRACE_SYSEMU_SINGLESTEP 32
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/* MTE allocation tag access */
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#define PTRACE_PEEKMTETAGS 33
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#define PTRACE_POKEMTETAGS 34
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#ifndef __ASSEMBLY__
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/*
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* User structures for general purpose, floating point and debug registers.
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*/
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struct user_pt_regs {
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__u64 regs[31];
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__u64 sp;
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__u64 pc;
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__u64 pstate;
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};
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struct user_fpsimd_state {
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__uint128_t vregs[32];
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__u32 fpsr;
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__u32 fpcr;
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__u32 __reserved[2];
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};
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struct user_hwdebug_state {
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__u32 dbg_info;
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__u32 pad;
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struct {
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__u64 addr;
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__u32 ctrl;
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__u32 pad;
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} dbg_regs[16];
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};
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/* SVE/FP/SIMD state (NT_ARM_SVE & NT_ARM_SSVE) */
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struct user_sve_header {
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__u32 size; /* total meaningful regset content in bytes */
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__u32 max_size; /* maxmium possible size for this thread */
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__u16 vl; /* current vector length */
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__u16 max_vl; /* maximum possible vector length */
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__u16 flags;
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__u16 __reserved;
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};
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/* Definitions for user_sve_header.flags: */
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#define SVE_PT_REGS_MASK (1 << 0)
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#define SVE_PT_REGS_FPSIMD 0
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#define SVE_PT_REGS_SVE SVE_PT_REGS_MASK
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/*
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* Common SVE_PT_* flags:
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* These must be kept in sync with prctl interface in <linux/prctl.h>
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*/
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#define SVE_PT_VL_INHERIT ((1 << 17) /* PR_SVE_VL_INHERIT */ >> 16)
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#define SVE_PT_VL_ONEXEC ((1 << 18) /* PR_SVE_SET_VL_ONEXEC */ >> 16)
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/*
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* The remainder of the SVE state follows struct user_sve_header. The
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* total size of the SVE state (including header) depends on the
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* metadata in the header: SVE_PT_SIZE(vq, flags) gives the total size
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* of the state in bytes, including the header.
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*
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* Refer to <asm/sigcontext.h> for details of how to pass the correct
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* "vq" argument to these macros.
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*/
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/* Offset from the start of struct user_sve_header to the register data */
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#define SVE_PT_REGS_OFFSET \
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((sizeof(struct user_sve_header) + (__SVE_VQ_BYTES - 1)) \
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/ __SVE_VQ_BYTES * __SVE_VQ_BYTES)
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/*
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* The register data content and layout depends on the value of the
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* flags field.
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*/
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/*
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* (flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD case:
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*
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* The payload starts at offset SVE_PT_FPSIMD_OFFSET, and is of type
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* struct user_fpsimd_state. Additional data might be appended in the
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* future: use SVE_PT_FPSIMD_SIZE(vq, flags) to compute the total size.
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* SVE_PT_FPSIMD_SIZE(vq, flags) will never be less than
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* sizeof(struct user_fpsimd_state).
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*/
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#define SVE_PT_FPSIMD_OFFSET SVE_PT_REGS_OFFSET
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#define SVE_PT_FPSIMD_SIZE(vq, flags) (sizeof(struct user_fpsimd_state))
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/*
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* (flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE case:
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*
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* The payload starts at offset SVE_PT_SVE_OFFSET, and is of size
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* SVE_PT_SVE_SIZE(vq, flags).
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*
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* Additional macros describe the contents and layout of the payload.
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* For each, SVE_PT_SVE_x_OFFSET(args) is the start offset relative to
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* the start of struct user_sve_header, and SVE_PT_SVE_x_SIZE(args) is
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* the size in bytes:
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*
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* x type description
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* - ---- -----------
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* ZREGS \
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* ZREG |
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* PREGS | refer to <asm/sigcontext.h>
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* PREG |
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* FFR /
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*
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* FPSR uint32_t FPSR
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* FPCR uint32_t FPCR
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*
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* Additional data might be appended in the future.
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*
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* The Z-, P- and FFR registers are represented in memory in an endianness-
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* invariant layout which differs from the layout used for the FPSIMD
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* V-registers on big-endian systems: see sigcontext.h for more explanation.
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*/
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#define SVE_PT_SVE_ZREG_SIZE(vq) __SVE_ZREG_SIZE(vq)
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#define SVE_PT_SVE_PREG_SIZE(vq) __SVE_PREG_SIZE(vq)
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#define SVE_PT_SVE_FFR_SIZE(vq) __SVE_FFR_SIZE(vq)
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#define SVE_PT_SVE_FPSR_SIZE sizeof(__u32)
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#define SVE_PT_SVE_FPCR_SIZE sizeof(__u32)
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#define SVE_PT_SVE_OFFSET SVE_PT_REGS_OFFSET
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#define SVE_PT_SVE_ZREGS_OFFSET \
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(SVE_PT_REGS_OFFSET + __SVE_ZREGS_OFFSET)
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#define SVE_PT_SVE_ZREG_OFFSET(vq, n) \
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(SVE_PT_REGS_OFFSET + __SVE_ZREG_OFFSET(vq, n))
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#define SVE_PT_SVE_ZREGS_SIZE(vq) \
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(SVE_PT_SVE_ZREG_OFFSET(vq, __SVE_NUM_ZREGS) - SVE_PT_SVE_ZREGS_OFFSET)
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#define SVE_PT_SVE_PREGS_OFFSET(vq) \
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(SVE_PT_REGS_OFFSET + __SVE_PREGS_OFFSET(vq))
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#define SVE_PT_SVE_PREG_OFFSET(vq, n) \
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(SVE_PT_REGS_OFFSET + __SVE_PREG_OFFSET(vq, n))
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#define SVE_PT_SVE_PREGS_SIZE(vq) \
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(SVE_PT_SVE_PREG_OFFSET(vq, __SVE_NUM_PREGS) - \
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SVE_PT_SVE_PREGS_OFFSET(vq))
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/* For streaming mode SVE (SSVE) FFR must be read and written as zero */
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#define SVE_PT_SVE_FFR_OFFSET(vq) \
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(SVE_PT_REGS_OFFSET + __SVE_FFR_OFFSET(vq))
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#define SVE_PT_SVE_FPSR_OFFSET(vq) \
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((SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq) + \
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(__SVE_VQ_BYTES - 1)) \
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/ __SVE_VQ_BYTES * __SVE_VQ_BYTES)
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#define SVE_PT_SVE_FPCR_OFFSET(vq) \
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(SVE_PT_SVE_FPSR_OFFSET(vq) + SVE_PT_SVE_FPSR_SIZE)
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/*
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* Any future extension appended after FPCR must be aligned to the next
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* 128-bit boundary.
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*/
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#define SVE_PT_SVE_SIZE(vq, flags) \
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((SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE \
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- SVE_PT_SVE_OFFSET + (__SVE_VQ_BYTES - 1)) \
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/ __SVE_VQ_BYTES * __SVE_VQ_BYTES)
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#define SVE_PT_SIZE(vq, flags) \
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(((flags) & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE ? \
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SVE_PT_SVE_OFFSET + SVE_PT_SVE_SIZE(vq, flags) \
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: ((((flags) & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD ? \
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SVE_PT_FPSIMD_OFFSET + SVE_PT_FPSIMD_SIZE(vq, flags) \
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: SVE_PT_REGS_OFFSET)))
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/* pointer authentication masks (NT_ARM_PAC_MASK) */
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struct user_pac_mask {
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__u64 data_mask;
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__u64 insn_mask;
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};
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/* pointer authentication keys (NT_ARM_PACA_KEYS, NT_ARM_PACG_KEYS) */
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struct user_pac_address_keys {
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__uint128_t apiakey;
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__uint128_t apibkey;
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__uint128_t apdakey;
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__uint128_t apdbkey;
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};
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struct user_pac_generic_keys {
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__uint128_t apgakey;
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};
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/* ZA state (NT_ARM_ZA) */
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struct user_za_header {
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__u32 size; /* total meaningful regset content in bytes */
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__u32 max_size; /* maxmium possible size for this thread */
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__u16 vl; /* current vector length */
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__u16 max_vl; /* maximum possible vector length */
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__u16 flags;
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__u16 __reserved;
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};
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/*
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* Common ZA_PT_* flags:
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* These must be kept in sync with prctl interface in <linux/prctl.h>
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*/
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#define ZA_PT_VL_INHERIT ((1 << 17) /* PR_SME_VL_INHERIT */ >> 16)
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#define ZA_PT_VL_ONEXEC ((1 << 18) /* PR_SME_SET_VL_ONEXEC */ >> 16)
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/*
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* The remainder of the ZA state follows struct user_za_header. The
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* total size of the ZA state (including header) depends on the
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* metadata in the header: ZA_PT_SIZE(vq, flags) gives the total size
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* of the state in bytes, including the header.
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*
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* Refer to <asm/sigcontext.h> for details of how to pass the correct
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* "vq" argument to these macros.
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*/
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/* Offset from the start of struct user_za_header to the register data */
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#define ZA_PT_ZA_OFFSET \
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((sizeof(struct user_za_header) + (__SVE_VQ_BYTES - 1)) \
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/ __SVE_VQ_BYTES * __SVE_VQ_BYTES)
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/*
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* The payload starts at offset ZA_PT_ZA_OFFSET, and is of size
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* ZA_PT_ZA_SIZE(vq, flags).
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*
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* The ZA array is stored as a sequence of horizontal vectors ZAV of SVL/8
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* bytes each, starting from vector 0.
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*
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* Additional data might be appended in the future.
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*
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* The ZA matrix is represented in memory in an endianness-invariant layout
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* which differs from the layout used for the FPSIMD V-registers on big-endian
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* systems: see sigcontext.h for more explanation.
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*/
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#define ZA_PT_ZAV_OFFSET(vq, n) \
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(ZA_PT_ZA_OFFSET + ((vq * __SVE_VQ_BYTES) * n))
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#define ZA_PT_ZA_SIZE(vq) ((vq * __SVE_VQ_BYTES) * (vq * __SVE_VQ_BYTES))
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#define ZA_PT_SIZE(vq) \
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(ZA_PT_ZA_OFFSET + ZA_PT_ZA_SIZE(vq))
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#endif /* __ASSEMBLY__ */
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#endif /* _UAPI__ASM_PTRACE_H */
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