linux-stable/arch/riscv/kernel
Linus Torvalds 5b1f3dc927 Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner:
 "The usual pile of boring changes:

   - Consolidate tasklet functions to share code instead of duplicating
     it

   - The first step for making the low level entry handler management on
     multi-platform kernels generic

   - A new sysfs file which allows to retrieve the wakeup state of
     interrupts.

   - Ensure that the interrupt thread follows the effective affinity and
     not the programmed affinity to avoid cross core wakeups.

   - Two new interrupt controller drivers (Microsemi Ocelot and Qualcomm
     PDC)

   - Fix the wakeup path clock handling for Reneasas interrupt chips.

   - Rework the boot time register reset for ARM GIC-V2/3

   - Better suspend/resume support for ARM GIV-V3/ITS

   - Add missing locking to the ARM GIC set_type() callback

   - Small fixes for the irq simulator code

   - SPDX identifiers for the irq core code and removal of boiler plate

   - Small cleanups all over the place"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (37 commits)
  openrisc: Set CONFIG_MULTI_IRQ_HANDLER
  arm64: Set CONFIG_MULTI_IRQ_HANDLER
  genirq: Make GENERIC_IRQ_MULTI_HANDLER depend on !MULTI_IRQ_HANDLER
  irqchip/gic: Take lock when updating irq type
  irqchip/gic: Update supports_deactivate static key to modern api
  irqchip/gic-v3: Ensure GICR_CTLR.EnableLPI=0 is observed before enabling
  irqchip: Add a driver for the Microsemi Ocelot controller
  dt-bindings: interrupt-controller: Add binding for the Microsemi Ocelot interrupt controller
  irqchip/gic-v3: Probe for SCR_EL3 being clear before resetting AP0Rn
  irqchip/gic-v3: Don't try to reset AP0Rn
  irqchip/gic-v3: Do not check trigger configuration of partitionned LPIs
  genirq: Remove license boilerplate/references
  genirq: Add missing SPDX identifiers
  genirq/matrix: Cleanup SPDX identifier
  genirq: Cleanup top of file comments
  genirq: Pass desc to __irq_free instead of irq number
  irqchip/gic-v3: Loudly complain about the use of IRQ_TYPE_NONE
  irqchip/gic: Loudly complain about the use of IRQ_TYPE_NONE
  RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler
  genirq: Add CONFIG_GENERIC_IRQ_MULTI_HANDLER
  ...
2018-04-04 15:19:26 -07:00
..
vdso RISC-V: Make __NR_riscv_flush_icache visible to userspace 2018-01-07 15:14:37 -08:00
.gitignore RISC-V: Build Infrastructure 2017-09-26 15:26:49 -07:00
asm-offsets.c RISC-V: Task implementation 2017-09-26 15:26:46 -07:00
cacheinfo.c
cpu.c
cpufeature.c RISC-V: User-facing API 2017-09-26 15:26:48 -07:00
entry.S RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler 2018-03-14 21:46:29 +01:00
ftrace.c riscv/ftrace: Add basic support 2018-01-30 19:10:54 -08:00
head.S Rename sbi_save to parse_dtb to improve code readability 2018-02-20 10:56:26 -08:00
irq.c RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler 2018-03-14 21:46:29 +01:00
Makefile riscv/ftrace: Add basic support 2018-01-30 19:10:54 -08:00
mcount.S riscv/ftrace: Add basic support 2018-01-30 19:10:54 -08:00
module.c RISC-V: User-facing API 2017-09-26 15:26:48 -07:00
process.c Merge branch 'work.whack-a-mole' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs 2018-01-31 19:18:12 -08:00
ptrace.c RISC-V: User-facing API 2017-09-26 15:26:48 -07:00
reset.c
riscv_ksyms.c RISC-V: Export some expected symbols for modules 2017-11-30 10:01:10 -08:00
setup.c Rename sbi_save to parse_dtb to improve code readability 2018-02-20 10:56:26 -08:00
signal.c RISC-V: User-facing API 2017-09-26 15:26:48 -07:00
smp.c RISC-V: Fixes for clean allmodconfig build 2017-12-01 13:31:31 -08:00
smpboot.c
stacktrace.c
sys_riscv.c mm: add ksys_mmap_pgoff() helper; remove in-kernel calls to sys_mmap_pgoff() 2018-04-02 20:16:11 +02:00
syscall_table.c RISC-V: Make __NR_riscv_flush_icache visible to userspace 2018-01-07 15:14:37 -08:00
time.c
traps.c
vdso.c riscv: remove redundant unlikely() 2018-01-30 19:12:06 -08:00
vmlinux.lds.S RISC-V: Build Infrastructure 2017-09-26 15:26:49 -07:00