mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-31 16:38:12 +00:00
1f7ad57b75
This patch contains the ia64 architecture specific changes to prevent the possible race conditions. Signed-off-by: Prasanna S Panchamukhi <prasanna@in.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
62 lines
1.4 KiB
ArmAsm
62 lines
1.4 KiB
ArmAsm
/*
|
|
* Cache flushing routines.
|
|
*
|
|
* Copyright (C) 1999-2001, 2005 Hewlett-Packard Co
|
|
* David Mosberger-Tang <davidm@hpl.hp.com>
|
|
*
|
|
* 05/28/05 Zoltan Menyhart Dynamic stride size
|
|
*/
|
|
|
|
#include <asm/asmmacro.h>
|
|
|
|
|
|
/*
|
|
* flush_icache_range(start,end)
|
|
*
|
|
* Make i-cache(s) coherent with d-caches.
|
|
*
|
|
* Must deal with range from start to end-1 but nothing else (need to
|
|
* be careful not to touch addresses that may be unmapped).
|
|
*
|
|
* Note: "in0" and "in1" are preserved for debugging purposes.
|
|
*/
|
|
.section .kprobes.text,"ax"
|
|
GLOBAL_ENTRY(flush_icache_range)
|
|
|
|
.prologue
|
|
alloc r2=ar.pfs,2,0,0,0
|
|
movl r3=ia64_i_cache_stride_shift
|
|
mov r21=1
|
|
;;
|
|
ld8 r20=[r3] // r20: stride shift
|
|
sub r22=in1,r0,1 // last byte address
|
|
;;
|
|
shr.u r23=in0,r20 // start / (stride size)
|
|
shr.u r22=r22,r20 // (last byte address) / (stride size)
|
|
shl r21=r21,r20 // r21: stride size of the i-cache(s)
|
|
;;
|
|
sub r8=r22,r23 // number of strides - 1
|
|
shl r24=r23,r20 // r24: addresses for "fc.i" =
|
|
// "start" rounded down to stride boundary
|
|
.save ar.lc,r3
|
|
mov r3=ar.lc // save ar.lc
|
|
;;
|
|
|
|
.body
|
|
mov ar.lc=r8
|
|
;;
|
|
/*
|
|
* 32 byte aligned loop, even number of (actually 2) bundles
|
|
*/
|
|
.Loop: fc.i r24 // issuable on M0 only
|
|
add r24=r21,r24 // we flush "stride size" bytes per iteration
|
|
nop.i 0
|
|
br.cloop.sptk.few .Loop
|
|
;;
|
|
sync.i
|
|
;;
|
|
srlz.i
|
|
;;
|
|
mov ar.lc=r3 // restore ar.lc
|
|
br.ret.sptk.many rp
|
|
END(flush_icache_range)
|