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bd5050e38a
When relaxing access (read -> read_write update), pte needs to be marked invalid to handle a nest MMU bug. We also need to do a tlb flush after the pte is marked invalid before updating the pte with new access bits. We also move tlb flush to platform specific __ptep_set_access_flags. This will help us to gerid of unnecessary tlb flush on BOOK3S 64 later. We don't do that in this patch. This also helps in avoiding multiple tlbies with coprocessor attached. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
86 lines
2.4 KiB
C
86 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_PGTABLE_H
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#define _ASM_POWERPC_PGTABLE_H
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#ifndef __ASSEMBLY__
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#include <linux/mmdebug.h>
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#include <linux/mmzone.h>
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#include <asm/processor.h> /* For TASK_SIZE */
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#include <asm/mmu.h>
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#include <asm/page.h>
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#include <asm/tlbflush.h>
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struct mm_struct;
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#endif /* !__ASSEMBLY__ */
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#ifdef CONFIG_PPC_BOOK3S
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#include <asm/book3s/pgtable.h>
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#else
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#include <asm/nohash/pgtable.h>
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#endif /* !CONFIG_PPC_BOOK3S */
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#ifndef __ASSEMBLY__
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#include <asm/tlbflush.h>
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/* Keep these as a macros to avoid include dependency mess */
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#define pte_page(x) pfn_to_page(pte_pfn(x))
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#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
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/*
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* ZERO_PAGE is a global shared page that is always zero: used
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* for zero-mapped memory areas etc..
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*/
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extern unsigned long empty_zero_page[];
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#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
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extern pgd_t swapper_pg_dir[];
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void limit_zone_pfn(enum zone_type zone, unsigned long max_pfn);
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int dma_pfn_limit_to_zone(u64 pfn_limit);
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extern void paging_init(void);
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/*
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* kern_addr_valid is intended to indicate whether an address is a valid
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* kernel address. Most 32-bit archs define it as always true (like this)
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* but most 64-bit archs actually perform a test. What should we do here?
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*/
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#define kern_addr_valid(addr) (1)
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#include <asm-generic/pgtable.h>
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/*
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* This gets called at the end of handling a page fault, when
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* the kernel has put a new PTE into the page table for the process.
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* We use it to ensure coherency between the i-cache and d-cache
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* for the page which has just been mapped in.
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* On machines which use an MMU hash table, we use this to put a
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* corresponding HPTE into the hash table ahead of time, instead of
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* waiting for the inevitable extra hash-table miss exception.
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*/
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extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
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extern int gup_hugepte(pte_t *ptep, unsigned long sz, unsigned long addr,
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unsigned long end, int write,
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struct page **pages, int *nr);
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#ifndef CONFIG_TRANSPARENT_HUGEPAGE
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#define pmd_large(pmd) 0
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#endif
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/* can we use this in kvm */
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unsigned long vmalloc_to_phys(void *vmalloc_addr);
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void pgtable_cache_add(unsigned shift, void (*ctor)(void *));
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void pgtable_cache_init(void);
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#if defined(CONFIG_STRICT_KERNEL_RWX) || defined(CONFIG_PPC32)
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void mark_initmem_nx(void);
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#else
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static inline void mark_initmem_nx(void) { }
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_POWERPC_PGTABLE_H */
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