mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-28 21:33:52 +00:00
75f66813e0
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
If both the HTTP and HTTPS versions
return 200 OK and serve the same content:
Replace HTTP with HTTPS.
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
95 lines
2.5 KiB
Text
95 lines
2.5 KiB
Text
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/*
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* VScom OnRISC
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* http://www.vscom.de
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*/
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/dts-v1/;
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#include "am335x-baltos.dtsi"
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#include "am335x-baltos-leds.dtsi"
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/ {
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model = "NetCom Plus";
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};
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&am33xx_pinmux {
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uart1_pins: pinmux_uart1_pins {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) /* RX */
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AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) /* TX */
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AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) /* CTS */
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AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* RTS */
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AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* DTR */
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AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DSR */
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AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DCD */
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AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* RI */
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>;
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};
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uart2_pins: pinmux_uart2_pins {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* RX */
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AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* TX */
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AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* CTS */
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AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* RTS */
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* DTR */
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DSR */
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DCD */
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* RI */
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>;
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};
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};
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&usb0_phy {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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dr_mode = "host";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
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dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
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dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
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rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
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dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
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dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
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rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&davinci_mdio {
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phy0: ethernet-phy@0 {
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reg = <1>;
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};
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};
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&cpsw_emac0 {
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phy-mode = "rmii";
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dual_emac_res_vlan = <1>;
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phy-handle = <&phy0>;
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};
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&cpsw_emac1 {
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phy-mode = "rgmii-id";
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dual_emac_res_vlan = <2>;
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phy-handle = <&phy1>;
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};
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