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a894c6dd56
The SP805 binding sets the name for the actual watchdog clock to "wdog_clk" (with an underscore). Change the name in the DTs for ARM Ltd. platforms to match that. The Linux and U-Boot driver use the *first* clock for this purpose anyway, so it does not break anything. For MPS2 we only specify one clock so far, but the binding requires two clocks to be named. In practice, Linux would pick a clock named "apb_pclk" for the bus clock, and the Linux and U-Boot SP805 driver would use the first clock to derive the actual watchdog counter frequency. So since currently both are the very same clock, we can just double the clock reference, and add the correct clock-names, to match the binding. Link: https://lore.kernel.org/r/20200828130602.42203-8-andre.przywara@arm.com Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
310 lines
6.7 KiB
Text
310 lines
6.7 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* ARM Ltd. Versatile Express
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*
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* CoreTile Express A15x2 (version with Test Chip 1)
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* Cortex-A15 MPCore (V2P-CA15)
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*
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* HBI-0237A
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*/
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/dts-v1/;
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#include "vexpress-v2m-rs1.dtsi"
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/ {
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model = "V2P-CA15";
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arm,hbi = <0x237>;
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arm,vexpress,site = <0xf>;
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compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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aliases {
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serial0 = &v2m_serial0;
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serial1 = &v2m_serial1;
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serial2 = &v2m_serial2;
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serial3 = &v2m_serial3;
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i2c0 = &v2m_i2c_dvi;
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i2c1 = &v2m_i2c_pcie;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0 0x80000000 0 0x40000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* Chipselect 2 is physically at 0x18000000 */
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vram: vram@18000000 {
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/* 8 MB of designated video RAM */
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compatible = "shared-dma-pool";
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reg = <0 0x18000000 0 0x00800000>;
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no-map;
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};
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};
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hdlcd@2b000000 {
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compatible = "arm,hdlcd";
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reg = <0 0x2b000000 0 0x1000>;
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interrupts = <0 85 4>;
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clocks = <&hdlcd_clk>;
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clock-names = "pxlclk";
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};
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memory-controller@2b0a0000 {
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compatible = "arm,pl341", "arm,primecell";
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reg = <0 0x2b0a0000 0 0x1000>;
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clocks = <&sys_pll>;
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clock-names = "apb_pclk";
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};
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wdt@2b060000 {
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compatible = "arm,sp805", "arm,primecell";
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status = "disabled";
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reg = <0 0x2b060000 0 0x1000>;
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interrupts = <0 98 4>;
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clocks = <&sys_pll>, <&sys_pll>;
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clock-names = "wdog_clk", "apb_pclk";
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};
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gic: interrupt-controller@2c001000 {
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compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0x2c001000 0 0x1000>,
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<0 0x2c002000 0 0x2000>,
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<0 0x2c004000 0 0x2000>,
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<0 0x2c006000 0 0x2000>;
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interrupts = <1 9 0xf04>;
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};
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memory-controller@7ffd0000 {
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compatible = "arm,pl354", "arm,primecell";
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reg = <0 0x7ffd0000 0 0x1000>;
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interrupts = <0 86 4>,
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<0 87 4>;
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clocks = <&sys_pll>;
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clock-names = "apb_pclk";
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};
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dma@7ffb0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0 0x7ffb0000 0 0x1000>;
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interrupts = <0 92 4>,
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<0 88 4>,
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<0 89 4>,
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<0 90 4>,
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<0 91 4>;
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clocks = <&sys_pll>;
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clock-names = "apb_pclk";
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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};
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pmu {
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compatible = "arm,cortex-a15-pmu";
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interrupts = <0 68 4>,
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<0 69 4>;
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};
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dcc {
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compatible = "arm,vexpress,config-bus";
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arm,vexpress,config-bridge = <&v2m_sysreg>;
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oscclk0 {
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/* CPU PLL reference clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 0>;
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freq-range = <50000000 60000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk0";
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};
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oscclk4 {
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/* Multiplexed AXI master clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 4>;
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freq-range = <20000000 40000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk4";
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};
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hdlcd_clk: oscclk5 {
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/* HDLCD PLL reference clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 5>;
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freq-range = <23750000 165000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk5";
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};
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smbclk: oscclk6 {
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/* SMB clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 6>;
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freq-range = <20000000 50000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk6";
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};
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sys_pll: oscclk7 {
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/* SYS PLL reference clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 7>;
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freq-range = <20000000 60000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk7";
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};
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oscclk8 {
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/* DDR2 PLL reference clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 8>;
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freq-range = <40000000 40000000>;
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#clock-cells = <0>;
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clock-output-names = "oscclk8";
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};
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volt-cores {
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/* CPU core voltage */
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compatible = "arm,vexpress-volt";
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arm,vexpress-sysreg,func = <2 0>;
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regulator-name = "Cores";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1050000>;
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regulator-always-on;
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label = "Cores";
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};
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amp-cores {
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/* Total current for the two cores */
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compatible = "arm,vexpress-amp";
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arm,vexpress-sysreg,func = <3 0>;
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label = "Cores";
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};
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temp-dcc {
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/* DCC internal temperature */
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compatible = "arm,vexpress-temp";
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arm,vexpress-sysreg,func = <4 0>;
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label = "DCC";
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};
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power-cores {
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/* Total power */
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compatible = "arm,vexpress-power";
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arm,vexpress-sysreg,func = <12 0>;
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label = "Cores";
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};
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energy {
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/* Total energy */
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compatible = "arm,vexpress-energy";
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arm,vexpress-sysreg,func = <13 0>;
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label = "Cores";
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};
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};
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bus@8000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0 0x08000000 0x04000000>,
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<1 0 0 0x14000000 0x04000000>,
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<2 0 0 0x18000000 0x04000000>,
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<3 0 0 0x1c000000 0x04000000>,
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<4 0 0 0x0c000000 0x04000000>,
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<5 0 0 0x10000000 0x04000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 63>;
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interrupt-map = <0 0 0 &gic 0 0 4>,
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<0 0 1 &gic 0 1 4>,
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<0 0 2 &gic 0 2 4>,
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<0 0 3 &gic 0 3 4>,
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<0 0 4 &gic 0 4 4>,
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<0 0 5 &gic 0 5 4>,
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<0 0 6 &gic 0 6 4>,
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<0 0 7 &gic 0 7 4>,
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<0 0 8 &gic 0 8 4>,
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<0 0 9 &gic 0 9 4>,
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<0 0 10 &gic 0 10 4>,
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<0 0 11 &gic 0 11 4>,
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<0 0 12 &gic 0 12 4>,
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<0 0 13 &gic 0 13 4>,
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<0 0 14 &gic 0 14 4>,
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<0 0 15 &gic 0 15 4>,
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<0 0 16 &gic 0 16 4>,
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<0 0 17 &gic 0 17 4>,
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<0 0 18 &gic 0 18 4>,
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<0 0 19 &gic 0 19 4>,
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<0 0 20 &gic 0 20 4>,
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<0 0 21 &gic 0 21 4>,
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<0 0 22 &gic 0 22 4>,
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<0 0 23 &gic 0 23 4>,
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<0 0 24 &gic 0 24 4>,
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<0 0 25 &gic 0 25 4>,
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<0 0 26 &gic 0 26 4>,
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<0 0 27 &gic 0 27 4>,
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<0 0 28 &gic 0 28 4>,
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<0 0 29 &gic 0 29 4>,
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<0 0 30 &gic 0 30 4>,
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<0 0 31 &gic 0 31 4>,
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<0 0 32 &gic 0 32 4>,
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<0 0 33 &gic 0 33 4>,
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<0 0 34 &gic 0 34 4>,
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<0 0 35 &gic 0 35 4>,
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<0 0 36 &gic 0 36 4>,
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<0 0 37 &gic 0 37 4>,
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<0 0 38 &gic 0 38 4>,
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<0 0 39 &gic 0 39 4>,
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<0 0 40 &gic 0 40 4>,
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<0 0 41 &gic 0 41 4>,
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<0 0 42 &gic 0 42 4>;
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};
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site2: hsb@40000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x40000000 0x3fef0000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 3>;
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interrupt-map = <0 0 &gic 0 36 4>,
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<0 1 &gic 0 37 4>,
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<0 2 &gic 0 38 4>,
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<0 3 &gic 0 39 4>;
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};
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};
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