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5d5a971338
The I/O-APIC generates an MSI cycle with address/data bits taken from its Redirection Table Entry in some combination which used to make sense, but now is just a bunch of bits which get passed through in some seemingly arbitrary order. Instead of making IRQ remapping drivers directly frob the I/OA-PIC RTE, let them just do their job and generate an MSI message. The bit swizzling to turn that MSI message into the I/O-APIC's RTE is the same in all cases, since it's a function of the I/O-APIC hardware. The IRQ remappers have no real need to get involved with that. The only slight caveat is that the I/OAPIC is interpreting some of those fields too, and it does want the 'vector' field to be unique to make EOI work. The AMD IOMMU happens to put its IRTE index in the bits that the I/O-APIC thinks are the vector field, and accommodates this requirement by reserving the first 32 indices for the I/O-APIC. The Intel IOMMU doesn't actually use the bits that the I/O-APIC thinks are the vector field, so it fills in the 'pin' value there instead. [ tglx: Replaced the unreadably macro maze with the cleaned up RTE/msi_msg bitfields and added commentry to explain the mapping magic ] Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20201024213535.443185-22-dwmw2@infradead.org
168 lines
4.1 KiB
C
168 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Hyper-V stub IOMMU driver.
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*
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* Copyright (C) 2019, Microsoft, Inc.
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*
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* Author : Lan Tianyu <Tianyu.Lan@microsoft.com>
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*/
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/iommu.h>
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#include <linux/module.h>
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#include <asm/apic.h>
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#include <asm/cpu.h>
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#include <asm/hw_irq.h>
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#include <asm/io_apic.h>
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#include <asm/irq_remapping.h>
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#include <asm/hypervisor.h>
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#include "irq_remapping.h"
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#ifdef CONFIG_IRQ_REMAP
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/*
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* According 82093AA IO-APIC spec , IO APIC has a 24-entry Interrupt
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* Redirection Table. Hyper-V exposes one single IO-APIC and so define
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* 24 IO APIC remmapping entries.
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*/
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#define IOAPIC_REMAPPING_ENTRY 24
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static cpumask_t ioapic_max_cpumask = { CPU_BITS_NONE };
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static struct irq_domain *ioapic_ir_domain;
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static int hyperv_ir_set_affinity(struct irq_data *data,
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const struct cpumask *mask, bool force)
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{
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struct irq_data *parent = data->parent_data;
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struct irq_cfg *cfg = irqd_cfg(data);
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int ret;
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/* Return error If new irq affinity is out of ioapic_max_cpumask. */
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if (!cpumask_subset(mask, &ioapic_max_cpumask))
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return -EINVAL;
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ret = parent->chip->irq_set_affinity(parent, mask, force);
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if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
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return ret;
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send_cleanup_vector(cfg);
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return 0;
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}
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static struct irq_chip hyperv_ir_chip = {
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.name = "HYPERV-IR",
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.irq_ack = apic_ack_irq,
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.irq_set_affinity = hyperv_ir_set_affinity,
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};
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static int hyperv_irq_remapping_alloc(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs,
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void *arg)
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{
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struct irq_alloc_info *info = arg;
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struct irq_data *irq_data;
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struct irq_desc *desc;
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int ret = 0;
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if (!info || info->type != X86_IRQ_ALLOC_TYPE_IOAPIC || nr_irqs > 1)
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return -EINVAL;
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ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
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if (ret < 0)
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return ret;
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irq_data = irq_domain_get_irq_data(domain, virq);
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if (!irq_data) {
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irq_domain_free_irqs_common(domain, virq, nr_irqs);
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return -EINVAL;
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}
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irq_data->chip = &hyperv_ir_chip;
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/*
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* Hypver-V IO APIC irq affinity should be in the scope of
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* ioapic_max_cpumask because no irq remapping support.
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*/
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desc = irq_data_to_desc(irq_data);
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cpumask_copy(desc->irq_common_data.affinity, &ioapic_max_cpumask);
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return 0;
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}
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static void hyperv_irq_remapping_free(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs)
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{
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irq_domain_free_irqs_common(domain, virq, nr_irqs);
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}
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static const struct irq_domain_ops hyperv_ir_domain_ops = {
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.alloc = hyperv_irq_remapping_alloc,
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.free = hyperv_irq_remapping_free,
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};
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static int __init hyperv_prepare_irq_remapping(void)
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{
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struct fwnode_handle *fn;
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int i;
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if (!hypervisor_is_type(X86_HYPER_MS_HYPERV) ||
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!x2apic_supported())
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return -ENODEV;
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fn = irq_domain_alloc_named_id_fwnode("HYPERV-IR", 0);
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if (!fn)
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return -ENOMEM;
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ioapic_ir_domain =
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irq_domain_create_hierarchy(arch_get_ir_parent_domain(),
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0, IOAPIC_REMAPPING_ENTRY, fn,
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&hyperv_ir_domain_ops, NULL);
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if (!ioapic_ir_domain) {
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irq_domain_free_fwnode(fn);
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return -ENOMEM;
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}
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/*
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* Hyper-V doesn't provide irq remapping function for
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* IO-APIC and so IO-APIC only accepts 8-bit APIC ID.
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* Cpu's APIC ID is read from ACPI MADT table and APIC IDs
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* in the MADT table on Hyper-v are sorted monotonic increasingly.
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* APIC ID reflects cpu topology. There maybe some APIC ID
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* gaps when cpu number in a socket is not power of two. Prepare
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* max cpu affinity for IOAPIC irqs. Scan cpu 0-255 and set cpu
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* into ioapic_max_cpumask if its APIC ID is less than 256.
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*/
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for (i = min_t(unsigned int, num_possible_cpus() - 1, 255); i >= 0; i--)
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if (cpu_physical_id(i) < 256)
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cpumask_set_cpu(i, &ioapic_max_cpumask);
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return 0;
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}
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static int __init hyperv_enable_irq_remapping(void)
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{
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return IRQ_REMAP_X2APIC_MODE;
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}
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static struct irq_domain *hyperv_get_irq_domain(struct irq_alloc_info *info)
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{
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if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC_GET_PARENT)
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return ioapic_ir_domain;
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else
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return NULL;
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}
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struct irq_remap_ops hyperv_irq_remap_ops = {
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.prepare = hyperv_prepare_irq_remapping,
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.enable = hyperv_enable_irq_remapping,
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.get_irq_domain = hyperv_get_irq_domain,
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};
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#endif
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