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ba59c9b43c
The IEPCLK_MUX is present on all SoCs whereas the CORECLK_MUX is present only on AM65x SoCs and J721E. Add support for both these CLK muxes. This allows the clock rates and clock parents for these to be controlled through DT leveraging the clk infrastructure for configuring the default parents and rates. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
54 lines
1.3 KiB
C
54 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* PRU-ICSS sub-system specific definitions
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*
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* Copyright (C) 2014-2020 Texas Instruments Incorporated - http://www.ti.com/
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* Suman Anna <s-anna@ti.com>
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*/
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#ifndef _PRUSS_DRIVER_H_
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#define _PRUSS_DRIVER_H_
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#include <linux/types.h>
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/*
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* enum pruss_mem - PRUSS memory range identifiers
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*/
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enum pruss_mem {
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PRUSS_MEM_DRAM0 = 0,
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PRUSS_MEM_DRAM1,
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PRUSS_MEM_SHRD_RAM2,
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PRUSS_MEM_MAX,
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};
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/**
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* struct pruss_mem_region - PRUSS memory region structure
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* @va: kernel virtual address of the PRUSS memory region
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* @pa: physical (bus) address of the PRUSS memory region
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* @size: size of the PRUSS memory region
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*/
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struct pruss_mem_region {
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void __iomem *va;
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phys_addr_t pa;
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size_t size;
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};
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/**
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* struct pruss - PRUSS parent structure
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* @dev: pruss device pointer
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* @cfg_base: base iomap for CFG region
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* @cfg_regmap: regmap for config region
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* @mem_regions: data for each of the PRUSS memory regions
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* @core_clk_mux: clk handle for PRUSS CORE_CLK_MUX
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* @iep_clk_mux: clk handle for PRUSS IEP_CLK_MUX
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*/
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struct pruss {
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struct device *dev;
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void __iomem *cfg_base;
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struct regmap *cfg_regmap;
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struct pruss_mem_region mem_regions[PRUSS_MEM_MAX];
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struct clk *core_clk_mux;
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struct clk *iep_clk_mux;
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};
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#endif /* _PRUSS_DRIVER_H_ */
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