182 lines
8.4 KiB
ReStructuredText
182 lines
8.4 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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RISC-V Hardware Probing Interface
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---------------------------------
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The RISC-V hardware probing interface is based around a single syscall, which
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is defined in <asm/hwprobe.h>::
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struct riscv_hwprobe {
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__s64 key;
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__u64 value;
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};
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long sys_riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pair_count,
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size_t cpu_count, cpu_set_t *cpus,
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unsigned int flags);
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The arguments are split into three groups: an array of key-value pairs, a CPU
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set, and some flags. The key-value pairs are supplied with a count. Userspace
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must prepopulate the key field for each element, and the kernel will fill in the
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value if the key is recognized. If a key is unknown to the kernel, its key field
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will be cleared to -1, and its value set to 0. The CPU set is defined by
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CPU_SET(3). For value-like keys (eg. vendor/arch/impl), the returned value will
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be only be valid if all CPUs in the given set have the same value. Otherwise -1
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will be returned. For boolean-like keys, the value returned will be a logical
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AND of the values for the specified CPUs. Usermode can supply NULL for cpus and
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0 for cpu_count as a shortcut for all online CPUs. There are currently no flags,
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this value must be zero for future compatibility.
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On success 0 is returned, on failure a negative error code is returned.
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The following keys are defined:
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* :c:macro:`RISCV_HWPROBE_KEY_MVENDORID`: Contains the value of ``mvendorid``,
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as defined by the RISC-V privileged architecture specification.
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* :c:macro:`RISCV_HWPROBE_KEY_MARCHID`: Contains the value of ``marchid``, as
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defined by the RISC-V privileged architecture specification.
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* :c:macro:`RISCV_HWPROBE_KEY_MIMPLID`: Contains the value of ``mimplid``, as
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defined by the RISC-V privileged architecture specification.
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* :c:macro:`RISCV_HWPROBE_KEY_BASE_BEHAVIOR`: A bitmask containing the base
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user-visible behavior that this kernel supports. The following base user ABIs
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are defined:
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* :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: Support for rv32ima or
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rv64ima, as defined by version 2.2 of the user ISA and version 1.10 of the
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privileged ISA, with the following known exceptions (more exceptions may be
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added, but only if it can be demonstrated that the user ABI is not broken):
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* The ``fence.i`` instruction cannot be directly executed by userspace
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programs (it may still be executed in userspace via a
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kernel-controlled mechanism such as the vDSO).
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* :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions
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that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`:
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base system behavior.
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* :c:macro:`RISCV_HWPROBE_IMA_FD`: The F and D extensions are supported, as
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defined by commit cd20cee ("FMIN/FMAX now implement
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minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual.
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* :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined
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by version 2.2 of the RISC-V ISA manual.
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* :c:macro:`RISCV_HWPROBE_IMA_V`: The V extension is supported, as defined by
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version 1.0 of the RISC-V Vector extension manual.
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* :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is
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supported, as defined in version 1.0 of the Bit-Manipulation ISA
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extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as defined
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in version 1.0 of the Bit-Manipulation ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined
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in version 1.0 of the Bit-Manipulation ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as
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ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
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* :c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as defined
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in version 1.0 of the Bit-Manipulation ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZBKB` The Zbkb extension is supported, as
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defined in version 1.0 of the Scalar Crypto ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZBKC` The Zbkc extension is supported, as
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defined in version 1.0 of the Scalar Crypto ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZBKX` The Zbkx extension is supported, as
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defined in version 1.0 of the Scalar Crypto ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZKND` The Zknd extension is supported, as
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defined in version 1.0 of the Scalar Crypto ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZKNE` The Zkne extension is supported, as
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defined in version 1.0 of the Scalar Crypto ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZKNH` The Zknh extension is supported, as
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defined in version 1.0 of the Scalar Crypto ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZKSED` The Zksed extension is supported, as
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defined in version 1.0 of the Scalar Crypto ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZKSH` The Zksh extension is supported, as
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defined in version 1.0 of the Scalar Crypto ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as defined
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in version 1.0 of the Scalar Crypto ISA extensions.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvbb extension is supported as
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defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvbc extension is supported as
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defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvkb extension is supported as
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defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvkg extension is supported as
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defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Zvkned extension is supported as
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defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Zvknha extension is supported as
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defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Zvknhb extension is supported as
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defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Zvksed extension is supported as
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defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zvksh extension is supported as
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defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as
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defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
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* :c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is supported
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as defined in the RISC-V ISA manual.
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* :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is
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supported as defined in the RISC-V ISA manual.
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* :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0
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is supported as defined in the RISC-V ISA manual.
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* :c:macro:`RISCV_HWPROBE_EXT_ZVFH`: The Zvfh extension is supported as
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defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
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("Remove draft warnings from Zvfh[min]").
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* :c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`: The Zvfhmin extension is supported as
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defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
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("Remove draft warnings from Zvfh[min]").
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* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
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information about the selected set of processors.
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* :c:macro:`RISCV_HWPROBE_MISALIGNED_UNKNOWN`: The performance of misaligned
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accesses is unknown.
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* :c:macro:`RISCV_HWPROBE_MISALIGNED_EMULATED`: Misaligned accesses are
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emulated via software, either in or below the kernel. These accesses are
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always extremely slow.
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* :c:macro:`RISCV_HWPROBE_MISALIGNED_SLOW`: Misaligned accesses are slower
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than equivalent byte accesses. Misaligned accesses may be supported
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directly in hardware, or trapped and emulated by software.
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* :c:macro:`RISCV_HWPROBE_MISALIGNED_FAST`: Misaligned accesses are faster
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than equivalent byte accesses.
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* :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are
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not supported at all and will generate a misaligned address fault.
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* :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which
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represents the size of the Zicboz block in bytes.
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