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5e01e58578
This patch enables 1-Wire module for Phytec PCM-970 RDK. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
112 lines
2.3 KiB
Text
112 lines
2.3 KiB
Text
/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "imx27-phytec-phycore-som.dtsi"
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/ {
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model = "Phytec pcm970";
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compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27";
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};
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&cspi1 {
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fsl,spi-num-chipselects = <2>;
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cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
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<&gpio4 27 GPIO_ACTIVE_LOW>;
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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camgpio: pca9536@41 {
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compatible = "nxp,pca9536";
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reg = <0x41>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&iomuxc {
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imx27_phycore_rdk {
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pinctrl_i2c1: i2c1grp {
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/* Add pullup to DATA line */
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fsl,pins = <
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MX27_PAD_I2C_DATA__I2C_DATA 0x1
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MX27_PAD_I2C_CLK__I2C_CLK 0x0
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>;
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};
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pinctrl_owire1: owire1grp {
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fsl,pins = <
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MX27_PAD_RTCK__OWIRE 0x0
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX27_PAD_UART1_TXD__UART1_TXD 0x0
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MX27_PAD_UART1_RXD__UART1_RXD 0x0
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MX27_PAD_UART1_CTS__UART1_CTS 0x0
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MX27_PAD_UART1_RTS__UART1_RTS 0x0
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX27_PAD_UART2_TXD__UART2_TXD 0x0
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MX27_PAD_UART2_RXD__UART2_RXD 0x0
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MX27_PAD_UART2_CTS__UART2_CTS 0x0
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MX27_PAD_UART2_RTS__UART2_RTS 0x0
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>;
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};
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};
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};
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&owire {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_owire1>;
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status = "okay";
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};
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&sdhci2 {
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bus-width = <4>;
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cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
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wp-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
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vmmc-supply = <&vmmc1_reg>;
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status = "okay";
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};
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&uart1 {
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fsl,uart-has-rtscts;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&uart2 {
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fsl,uart-has-rtscts;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&weim {
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can@d4000000 {
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compatible = "nxp,sja1000";
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reg = <4 0x00000000 0x00000100>;
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interrupt-parent = <&gpio5>;
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interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
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nxp,external-clock-frequency = <16000000>;
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nxp,tx-output-config = <0x16>;
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nxp,no-comparator-bypass;
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fsl,weim-cs-timing = <0x0000dcf6 0x444a0301 0x44443302>;
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};
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};
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