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Our SoC branch usually contains expanded support for new SoCs and other core platform code. In this case, that includes: - Support for the new Annapurna Labs "Alpine" platform - A rework greatly simplifying adding new platform support to the MCPM subsystem (Multi-cluster power management) - Cpuidle and PM improvements for Exynos3250 - Misc updates for Renesas, OMAP, Meson, i.MX. Some of these could have gone in other branches but ended up here for various reasons. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJVNzfWAAoJEIwa5zzehBx3idcP/Rt042tqb0bian/4M1Ud1aQ7 AMRd4oU5MfWAlzaGPeMBS+b1eo/eENj6wyWsvBQIByZN76ImlUXtxsx0U0frLrVg mWVo9zOLRuoE6yyq329zZgg1IM1RtRIruS6zucKsHgKtq0DcjhYGGUH0ZVZk/rKI RLtRK8U6Jr0lnpu1TDE5mii7GCCZlEl5dG+J3w5ewC9y7RLRlM09xjK/Zsj0QOqY JvMOIaHuHMT6l7BQ6QajtVxTeGECOJ3YDqC6mDHCVD7f3v88+7H5C20xNGPK921w tLfB5qOojnj+kKZRPhi8EGnRzKwrBq6/mE5CvvigTCGlAEUOzy7PFSY9oNE80QeL 6mUdPTuZuqz7ZEIF0kj8I0AkB6k8B+aYfqA9mqM5yGpa11HvZZGfP7CwI4izoe6+ sT++0OeDPwbsMyRxZjqNQLs4QYaKGYMP4NCgA17zz5ToRCQZy7e5hd2GYzaRouyi kTpR9FbxwDcBIwTcA3F7oJ90BEMJ0tvGz/Al11UQpzPePhTwQt2yB5bRZyK/RYIU x8k8RHArG3fmS89D4aOViL3sy/zoUBedx4UfAo6jVbrvoZGALQL23KHdqBqDiPmP sMRj/sSr+0h9nJCVNM6I/OUD4/IrpFGaeX9V7rpEsHVe7j83eV7Q2wNRPyVTgxdn jS8TS0FNAXIv8FO9EoNH =tcGs -----END PGP SIGNATURE----- Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Olof Johansson: "Our SoC branch usually contains expanded support for new SoCs and other core platform code. In this case, that includes: - support for the new Annapurna Labs "Alpine" platform - a rework greatly simplifying adding new platform support to the MCPM subsystem (Multi-cluster power management) - cpuidle and PM improvements for Exynos3250 - misc updates for Renesas, OMAP, Meson, i.MX. Some of these could have gone in other branches but ended up here for various reasons" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (53 commits) ARM: alpine: add support for generic pci ARM: Exynos: migrate DCSCB to the new MCPM backend abstraction ARM: vexpress: migrate DCSCB to the new MCPM backend abstraction ARM: vexpress: DCSCB: tighten CPU validity assertion ARM: vexpress: migrate TC2 to the new MCPM backend abstraction ARM: MCPM: move the algorithmic complexity to the core code ARM: EXYNOS: allow cpuidle driver usage on Exynos3250 SoC ARM: EXYNOS: add AFTR mode support for Exynos3250 ARM: EXYNOS: add code for setting/clearing boot flag ARM: EXYNOS: fix CPU1 hotplug on Exynos3250 ARM: S3C64XX: Use fixed IRQ bases to avoid conflicts on Cragganmore ARM: cygnus: fix const declaration bcm_cygnus_dt_compat ARM: DRA7: hwmod: Fix the hwmod class for GPTimer4 ARM: DRA7: hwmod: Add data for GPTimers 13 through 16 ARM: EXYNOS: Remove left over 'extra_save' ARM: EXYNOS: Constify exynos_pm_data array ARM: EXYNOS: use static in suspend.c ARM: EXYNOS: Use platform device name as power domain name ARM: EXYNOS: add support for async-bridge clocks for pm_domains ARM: omap-device: add missed callback for suspend-to-disk ...
203 lines
5 KiB
C
203 lines
5 KiB
C
/*
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* R-Car Generation 2 support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Magnus Damm
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* Copyright (C) 2014 Ulrich Hecht
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk/shmobile.h>
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#include <linux/clocksource.h>
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#include <linux/device.h>
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#include <linux/dma-contiguous.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/memblock.h>
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#include <linux/of.h>
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#include <linux/of_fdt.h>
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#include <asm/mach/arch.h>
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#include "common.h"
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#include "rcar-gen2.h"
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#define MODEMR 0xe6160060
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u32 rcar_gen2_read_mode_pins(void)
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{
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static u32 mode;
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static bool mode_valid;
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if (!mode_valid) {
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void __iomem *modemr = ioremap_nocache(MODEMR, 4);
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BUG_ON(!modemr);
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mode = ioread32(modemr);
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iounmap(modemr);
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mode_valid = true;
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}
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return mode;
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}
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#define CNTCR 0
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#define CNTFID0 0x20
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void __init rcar_gen2_timer_init(void)
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{
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u32 mode = rcar_gen2_read_mode_pins();
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#ifdef CONFIG_ARM_ARCH_TIMER
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void __iomem *base;
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int extal_mhz = 0;
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u32 freq;
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if (of_machine_is_compatible("renesas,r8a7794")) {
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freq = 260000000 / 8; /* ZS / 8 */
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/* CNTVOFF has to be initialized either from non-secure
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* Hypervisor mode or secure Monitor mode with SCR.NS==1.
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* If TrustZone is enabled then it should be handled by the
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* secure code.
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*/
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asm volatile(
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" cps 0x16\n"
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" mrc p15, 0, r1, c1, c1, 0\n"
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" orr r0, r1, #1\n"
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" mcr p15, 0, r0, c1, c1, 0\n"
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" isb\n"
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" mov r0, #0\n"
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" mcrr p15, 4, r0, r0, c14\n"
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" isb\n"
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" mcr p15, 0, r1, c1, c1, 0\n"
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" isb\n"
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" cps 0x13\n"
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: : : "r0", "r1");
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} else {
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/* At Linux boot time the r8a7790 arch timer comes up
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* with the counter disabled. Moreover, it may also report
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* a potentially incorrect fixed 13 MHz frequency. To be
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* correct these registers need to be updated to use the
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* frequency EXTAL / 2 which can be determined by the MD pins.
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*/
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switch (mode & (MD(14) | MD(13))) {
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case 0:
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extal_mhz = 15;
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break;
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case MD(13):
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extal_mhz = 20;
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break;
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case MD(14):
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extal_mhz = 26;
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break;
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case MD(13) | MD(14):
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extal_mhz = 30;
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break;
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}
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/* The arch timer frequency equals EXTAL / 2 */
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freq = extal_mhz * (1000000 / 2);
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}
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/* Remap "armgcnt address map" space */
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base = ioremap(0xe6080000, PAGE_SIZE);
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/*
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* Update the timer if it is either not running, or is not at the
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* right frequency. The timer is only configurable in secure mode
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* so this avoids an abort if the loader started the timer and
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* entered the kernel in non-secure mode.
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*/
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if ((ioread32(base + CNTCR) & 1) == 0 ||
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ioread32(base + CNTFID0) != freq) {
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/* Update registers with correct frequency */
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iowrite32(freq, base + CNTFID0);
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asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
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/* make sure arch timer is started by setting bit 0 of CNTCR */
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iowrite32(1, base + CNTCR);
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}
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iounmap(base);
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#endif /* CONFIG_ARM_ARCH_TIMER */
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rcar_gen2_clocks_init(mode);
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#ifdef CONFIG_ARCH_SHMOBILE_MULTI
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clocksource_of_init();
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#endif
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}
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struct memory_reserve_config {
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u64 reserved;
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u64 base, size;
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};
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static int __init rcar_gen2_scan_mem(unsigned long node, const char *uname,
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int depth, void *data)
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{
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const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
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const __be32 *reg, *endp;
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int l;
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struct memory_reserve_config *mrc = data;
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u64 lpae_start = 1ULL << 32;
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/* We are scanning "memory" nodes only */
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if (type == NULL || strcmp(type, "memory"))
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return 0;
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reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l);
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if (reg == NULL)
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reg = of_get_flat_dt_prop(node, "reg", &l);
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if (reg == NULL)
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return 0;
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endp = reg + (l / sizeof(__be32));
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while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) {
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u64 base, size;
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base = dt_mem_next_cell(dt_root_addr_cells, ®);
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size = dt_mem_next_cell(dt_root_size_cells, ®);
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if (base >= lpae_start)
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continue;
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if ((base + size) >= lpae_start)
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size = lpae_start - base;
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if (size < mrc->reserved)
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continue;
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if (base < mrc->base)
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continue;
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/* keep the area at top near the 32-bit legacy limit */
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mrc->base = base + size - mrc->reserved;
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mrc->size = mrc->reserved;
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}
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return 0;
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}
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struct cma *rcar_gen2_dma_contiguous;
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void __init rcar_gen2_reserve(void)
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{
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struct memory_reserve_config mrc;
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/* reserve 256 MiB at the top of the physical legacy 32-bit space */
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memset(&mrc, 0, sizeof(mrc));
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mrc.reserved = SZ_256M;
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of_scan_flat_dt(rcar_gen2_scan_mem, &mrc);
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#ifdef CONFIG_DMA_CMA
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if (mrc.size && memblock_is_region_memory(mrc.base, mrc.size))
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dma_contiguous_reserve_area(mrc.size, mrc.base, 0,
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&rcar_gen2_dma_contiguous, true);
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#endif
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}
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