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![Jacky Bai](/assets/img/avatar_default.png)
Add 300MHz frequency config support on i.MX93 PLL. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-5-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
392 lines
9.7 KiB
C
392 lines
9.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2021 NXP
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*/
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#include <linux/bitfield.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/export.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/slab.h>
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#include <asm/div64.h>
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#include "clk.h"
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#define PLL_CTRL 0x0
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#define HW_CTRL_SEL BIT(16)
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#define CLKMUX_BYPASS BIT(2)
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#define CLKMUX_EN BIT(1)
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#define POWERUP_MASK BIT(0)
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#define PLL_ANA_PRG 0x10
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#define PLL_SPREAD_SPECTRUM 0x30
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#define PLL_NUMERATOR 0x40
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#define PLL_MFN_MASK GENMASK(31, 2)
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#define PLL_DENOMINATOR 0x50
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#define PLL_MFD_MASK GENMASK(29, 0)
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#define PLL_DIV 0x60
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#define PLL_MFI_MASK GENMASK(24, 16)
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#define PLL_RDIV_MASK GENMASK(15, 13)
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#define PLL_ODIV_MASK GENMASK(7, 0)
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#define PLL_DFS_CTRL(x) (0x70 + (x) * 0x10)
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#define PLL_STATUS 0xF0
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#define LOCK_STATUS BIT(0)
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#define DFS_STATUS 0xF4
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#define LOCK_TIMEOUT_US 200
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#define PLL_FRACN_GP(_rate, _mfi, _mfn, _mfd, _rdiv, _odiv) \
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{ \
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.rate = (_rate), \
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.mfi = (_mfi), \
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.mfn = (_mfn), \
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.mfd = (_mfd), \
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.rdiv = (_rdiv), \
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.odiv = (_odiv), \
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}
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#define PLL_FRACN_GP_INTEGER(_rate, _mfi, _rdiv, _odiv) \
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{ \
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.rate = (_rate), \
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.mfi = (_mfi), \
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.mfn = 0, \
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.mfd = 0, \
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.rdiv = (_rdiv), \
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.odiv = (_odiv), \
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}
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struct clk_fracn_gppll {
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struct clk_hw hw;
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void __iomem *base;
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const struct imx_fracn_gppll_rate_table *rate_table;
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int rate_count;
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u32 flags;
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};
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/*
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* Fvco = (Fref / rdiv) * (MFI + MFN / MFD)
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* Fout = Fvco / odiv
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* The (Fref / rdiv) should be in range 20MHz to 40MHz
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* The Fvco should be in range 2.5Ghz to 5Ghz
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*/
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static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
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PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6),
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PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
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PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6),
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PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),
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PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
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PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
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PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),
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PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10),
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PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12)
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};
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struct imx_fracn_gppll_clk imx_fracn_gppll = {
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.rate_table = fracn_tbl,
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.rate_count = ARRAY_SIZE(fracn_tbl),
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};
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EXPORT_SYMBOL_GPL(imx_fracn_gppll);
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/*
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* Fvco = (Fref / rdiv) * MFI
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* Fout = Fvco / odiv
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* The (Fref / rdiv) should be in range 20MHz to 40MHz
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* The Fvco should be in range 2.5Ghz to 5Ghz
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*/
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static const struct imx_fracn_gppll_rate_table int_tbl[] = {
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PLL_FRACN_GP_INTEGER(1700000000U, 141, 1, 2),
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PLL_FRACN_GP_INTEGER(1400000000U, 175, 1, 3),
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PLL_FRACN_GP_INTEGER(900000000U, 150, 1, 4),
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};
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struct imx_fracn_gppll_clk imx_fracn_gppll_integer = {
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.rate_table = int_tbl,
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.rate_count = ARRAY_SIZE(int_tbl),
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};
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EXPORT_SYMBOL_GPL(imx_fracn_gppll_integer);
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static inline struct clk_fracn_gppll *to_clk_fracn_gppll(struct clk_hw *hw)
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{
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return container_of(hw, struct clk_fracn_gppll, hw);
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}
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static const struct imx_fracn_gppll_rate_table *
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imx_get_pll_settings(struct clk_fracn_gppll *pll, unsigned long rate)
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{
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const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
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int i;
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for (i = 0; i < pll->rate_count; i++)
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if (rate == rate_table[i].rate)
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return &rate_table[i];
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return NULL;
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}
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static long clk_fracn_gppll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
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const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
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int i;
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/* Assuming rate_table is in descending order */
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for (i = 0; i < pll->rate_count; i++)
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if (rate >= rate_table[i].rate)
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return rate_table[i].rate;
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/* return minimum supported value */
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return rate_table[pll->rate_count - 1].rate;
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}
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static unsigned long clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
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const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
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u32 pll_numerator, pll_denominator, pll_div;
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u32 mfi, mfn, mfd, rdiv, odiv;
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u64 fvco = parent_rate;
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long rate = 0;
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int i;
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pll_numerator = readl_relaxed(pll->base + PLL_NUMERATOR);
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mfn = FIELD_GET(PLL_MFN_MASK, pll_numerator);
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pll_denominator = readl_relaxed(pll->base + PLL_DENOMINATOR);
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mfd = FIELD_GET(PLL_MFD_MASK, pll_denominator);
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pll_div = readl_relaxed(pll->base + PLL_DIV);
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mfi = FIELD_GET(PLL_MFI_MASK, pll_div);
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rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div);
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odiv = FIELD_GET(PLL_ODIV_MASK, pll_div);
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/*
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* Sometimes, the recalculated rate has deviation due to
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* the frac part. So find the accurate pll rate from the table
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* first, if no match rate in the table, use the rate calculated
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* from the equation below.
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*/
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for (i = 0; i < pll->rate_count; i++) {
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if (rate_table[i].mfn == mfn && rate_table[i].mfi == mfi &&
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rate_table[i].mfd == mfd && rate_table[i].rdiv == rdiv &&
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rate_table[i].odiv == odiv)
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rate = rate_table[i].rate;
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}
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if (rate)
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return (unsigned long)rate;
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if (!rdiv)
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rdiv = rdiv + 1;
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switch (odiv) {
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case 0:
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odiv = 2;
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break;
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case 1:
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odiv = 3;
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break;
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default:
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break;
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}
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if (pll->flags & CLK_FRACN_GPPLL_INTEGER) {
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/* Fvco = (Fref / rdiv) * MFI */
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fvco = fvco * mfi;
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do_div(fvco, rdiv * odiv);
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} else {
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/* Fvco = (Fref / rdiv) * (MFI + MFN / MFD) */
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fvco = fvco * mfi * mfd + fvco * mfn;
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do_div(fvco, mfd * rdiv * odiv);
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}
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return (unsigned long)fvco;
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}
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static int clk_fracn_gppll_wait_lock(struct clk_fracn_gppll *pll)
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{
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u32 val;
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return readl_poll_timeout(pll->base + PLL_STATUS, val,
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val & LOCK_STATUS, 0, LOCK_TIMEOUT_US);
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}
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static int clk_fracn_gppll_set_rate(struct clk_hw *hw, unsigned long drate,
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unsigned long prate)
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{
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struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
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const struct imx_fracn_gppll_rate_table *rate;
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u32 tmp, pll_div, ana_mfn;
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int ret;
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rate = imx_get_pll_settings(pll, drate);
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/* Hardware control select disable. PLL is control by register */
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tmp = readl_relaxed(pll->base + PLL_CTRL);
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tmp &= ~HW_CTRL_SEL;
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writel_relaxed(tmp, pll->base + PLL_CTRL);
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/* Disable output */
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tmp = readl_relaxed(pll->base + PLL_CTRL);
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tmp &= ~CLKMUX_EN;
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writel_relaxed(tmp, pll->base + PLL_CTRL);
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/* Power Down */
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tmp &= ~POWERUP_MASK;
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writel_relaxed(tmp, pll->base + PLL_CTRL);
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/* Disable BYPASS */
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tmp &= ~CLKMUX_BYPASS;
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writel_relaxed(tmp, pll->base + PLL_CTRL);
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pll_div = FIELD_PREP(PLL_RDIV_MASK, rate->rdiv) | rate->odiv |
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FIELD_PREP(PLL_MFI_MASK, rate->mfi);
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writel_relaxed(pll_div, pll->base + PLL_DIV);
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if (pll->flags & CLK_FRACN_GPPLL_FRACN) {
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writel_relaxed(rate->mfd, pll->base + PLL_DENOMINATOR);
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writel_relaxed(FIELD_PREP(PLL_MFN_MASK, rate->mfn), pll->base + PLL_NUMERATOR);
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}
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/* Wait for 5us according to fracn mode pll doc */
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udelay(5);
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/* Enable Powerup */
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tmp |= POWERUP_MASK;
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writel_relaxed(tmp, pll->base + PLL_CTRL);
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/* Wait Lock */
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ret = clk_fracn_gppll_wait_lock(pll);
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if (ret)
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return ret;
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/* Enable output */
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tmp |= CLKMUX_EN;
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writel_relaxed(tmp, pll->base + PLL_CTRL);
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ana_mfn = readl_relaxed(pll->base + PLL_STATUS);
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ana_mfn = FIELD_GET(PLL_MFN_MASK, ana_mfn);
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WARN(ana_mfn != rate->mfn, "ana_mfn != rate->mfn\n");
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return 0;
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}
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static int clk_fracn_gppll_prepare(struct clk_hw *hw)
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{
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struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
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u32 val;
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int ret;
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val = readl_relaxed(pll->base + PLL_CTRL);
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if (val & POWERUP_MASK)
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return 0;
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val |= CLKMUX_BYPASS;
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writel_relaxed(val, pll->base + PLL_CTRL);
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val |= POWERUP_MASK;
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writel_relaxed(val, pll->base + PLL_CTRL);
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val |= CLKMUX_EN;
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writel_relaxed(val, pll->base + PLL_CTRL);
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ret = clk_fracn_gppll_wait_lock(pll);
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if (ret)
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return ret;
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val &= ~CLKMUX_BYPASS;
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writel_relaxed(val, pll->base + PLL_CTRL);
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return 0;
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}
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static int clk_fracn_gppll_is_prepared(struct clk_hw *hw)
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{
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struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
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u32 val;
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val = readl_relaxed(pll->base + PLL_CTRL);
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return (val & POWERUP_MASK) ? 1 : 0;
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}
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static void clk_fracn_gppll_unprepare(struct clk_hw *hw)
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{
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struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
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u32 val;
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val = readl_relaxed(pll->base + PLL_CTRL);
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val &= ~POWERUP_MASK;
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writel_relaxed(val, pll->base + PLL_CTRL);
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}
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static const struct clk_ops clk_fracn_gppll_ops = {
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.prepare = clk_fracn_gppll_prepare,
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.unprepare = clk_fracn_gppll_unprepare,
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.is_prepared = clk_fracn_gppll_is_prepared,
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.recalc_rate = clk_fracn_gppll_recalc_rate,
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.round_rate = clk_fracn_gppll_round_rate,
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.set_rate = clk_fracn_gppll_set_rate,
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};
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static struct clk_hw *_imx_clk_fracn_gppll(const char *name, const char *parent_name,
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void __iomem *base,
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const struct imx_fracn_gppll_clk *pll_clk,
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u32 pll_flags)
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{
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struct clk_fracn_gppll *pll;
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struct clk_hw *hw;
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struct clk_init_data init;
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int ret;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.flags = pll_clk->flags;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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init.ops = &clk_fracn_gppll_ops;
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pll->base = base;
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pll->hw.init = &init;
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pll->rate_table = pll_clk->rate_table;
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pll->rate_count = pll_clk->rate_count;
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pll->flags = pll_flags;
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hw = &pll->hw;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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pr_err("%s: failed to register pll %s %d\n", __func__, name, ret);
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kfree(pll);
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return ERR_PTR(ret);
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}
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return hw;
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}
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struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base,
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const struct imx_fracn_gppll_clk *pll_clk)
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{
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return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_FRACN);
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}
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EXPORT_SYMBOL_GPL(imx_clk_fracn_gppll);
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struct clk_hw *imx_clk_fracn_gppll_integer(const char *name, const char *parent_name,
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void __iomem *base,
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const struct imx_fracn_gppll_clk *pll_clk)
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{
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return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_INTEGER);
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}
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EXPORT_SYMBOL_GPL(imx_clk_fracn_gppll_integer);
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