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a65615df5b
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert all mediatek clk drivers from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230430190233.878921-4-u.kleine-koenig@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
213 lines
6.5 KiB
C
213 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021 MediaTek Inc.
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* Chun-Jie Chen <chun-jie.chen@mediatek.com>
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* Copyright (c) 2023 Collabora Ltd.
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* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#include <dt-bindings/clock/mt8192-clk.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "clk-fhctl.h"
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include "clk-pll.h"
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#include "clk-pllfh.h"
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static const struct mtk_gate_regs apmixed_cg_regs = {
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.set_ofs = 0x14,
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.clr_ofs = 0x14,
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.sta_ofs = 0x14,
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};
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#define GATE_APMIXED(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
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static const struct mtk_gate apmixed_clks[] = {
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GATE_APMIXED(CLK_APMIXED_MIPID26M, "mipid26m", "clk26m", 16),
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};
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#define MT8192_PLL_FMAX (3800UL * MHZ)
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#define MT8192_PLL_FMIN (1500UL * MHZ)
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#define MT8192_INTEGER_BITS 8
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#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
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_rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
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_tuner_reg, _tuner_en_reg, _tuner_en_bit, \
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_pcw_reg, _pcw_shift, _pcw_chg_reg, \
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_en_reg, _pll_en_bit) { \
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.id = _id, \
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.name = _name, \
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.reg = _reg, \
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.pwr_reg = _pwr_reg, \
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.en_mask = _en_mask, \
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.flags = _flags, \
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.rst_bar_mask = _rst_bar_mask, \
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.fmax = MT8192_PLL_FMAX, \
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.fmin = MT8192_PLL_FMIN, \
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.pcwbits = _pcwbits, \
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.pcwibits = MT8192_INTEGER_BITS, \
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.pd_reg = _pd_reg, \
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.pd_shift = _pd_shift, \
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.tuner_reg = _tuner_reg, \
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.tuner_en_reg = _tuner_en_reg, \
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.tuner_en_bit = _tuner_en_bit, \
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.pcw_reg = _pcw_reg, \
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.pcw_shift = _pcw_shift, \
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.pcw_chg_reg = _pcw_chg_reg, \
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.en_reg = _en_reg, \
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.pll_en_bit = _pll_en_bit, \
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}
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#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
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_rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
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_tuner_reg, _tuner_en_reg, _tuner_en_bit, \
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_pcw_reg, _pcw_shift) \
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PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
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_rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
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_tuner_reg, _tuner_en_reg, _tuner_en_bit, \
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_pcw_reg, _pcw_shift, 0, 0, 0)
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static const struct mtk_pll_data plls[] = {
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PLL_B(CLK_APMIXED_MAINPLL, "mainpll", 0x0340, 0x034c, 0xff000000,
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HAVE_RST_BAR, BIT(23), 22, 0x0344, 24, 0, 0, 0, 0x0344, 0),
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PLL_B(CLK_APMIXED_UNIVPLL, "univpll", 0x0308, 0x0314, 0xff000000,
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HAVE_RST_BAR, BIT(23), 22, 0x030c, 24, 0, 0, 0, 0x030c, 0),
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PLL(CLK_APMIXED_USBPLL, "usbpll", 0x03c4, 0x03cc, 0x00000000,
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0, 0, 22, 0x03c4, 24, 0, 0, 0, 0x03c4, 0, 0x03c4, 0x03cc, 2),
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PLL_B(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035c, 0x00000000,
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0, 0, 22, 0x0354, 24, 0, 0, 0, 0x0354, 0),
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PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0360, 0x036c, 0xff000000,
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HAVE_RST_BAR, BIT(23), 22, 0x0364, 24, 0, 0, 0, 0x0364, 0),
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PLL_B(CLK_APMIXED_ADSPPLL, "adsppll", 0x0370, 0x037c, 0xff000000,
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HAVE_RST_BAR, BIT(23), 22, 0x0374, 24, 0, 0, 0, 0x0374, 0),
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PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0268, 0x0274, 0x00000000,
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0, 0, 22, 0x026c, 24, 0, 0, 0, 0x026c, 0),
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PLL_B(CLK_APMIXED_TVDPLL, "tvdpll", 0x0380, 0x038c, 0x00000000,
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0, 0, 22, 0x0384, 24, 0, 0, 0, 0x0384, 0),
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PLL_B(CLK_APMIXED_APLL1, "apll1", 0x0318, 0x0328, 0x00000000,
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0, 0, 32, 0x031c, 24, 0x0040, 0x000c, 0, 0x0320, 0),
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PLL_B(CLK_APMIXED_APLL2, "apll2", 0x032c, 0x033c, 0x00000000,
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0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0),
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};
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enum fh_pll_id {
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FH_ARMPLL_LL,
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FH_ARMPLL_BL0,
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FH_ARMPLL_BL1,
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FH_ARMPLL_BL2,
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FH_ARMPLL_BL3,
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FH_CCIPLL,
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FH_MFGPLL,
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FH_MEMPLL,
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FH_MPLL,
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FH_MMPLL,
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FH_MAINPLL,
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FH_MSDCPLL,
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FH_ADSPPLL,
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FH_APUPLL,
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FH_TVDPLL,
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FH_NR_FH,
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};
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#define FH(_pllid, _fhid, _offset) { \
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.data = { \
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.pll_id = _pllid, \
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.fh_id = _fhid, \
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.fh_ver = FHCTL_PLLFH_V2, \
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.fhx_offset = _offset, \
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.dds_mask = GENMASK(21, 0), \
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.slope0_value = 0x6003c97, \
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.slope1_value = 0x6003c97, \
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.sfstrx_en = BIT(2), \
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.frddsx_en = BIT(1), \
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.fhctlx_en = BIT(0), \
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.tgl_org = BIT(31), \
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.dvfs_tri = BIT(31), \
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.pcwchg = BIT(31), \
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.dt_val = 0x0, \
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.df_val = 0x9, \
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.updnlmt_shft = 16, \
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.msk_frddsx_dys = GENMASK(23, 20), \
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.msk_frddsx_dts = GENMASK(19, 16), \
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}, \
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}
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static struct mtk_pllfh_data pllfhs[] = {
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FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0xb4),
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FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0),
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FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104),
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FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118),
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FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x12c),
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FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0x154),
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};
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static const struct of_device_id of_match_clk_mt8192_apmixed[] = {
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{ .compatible = "mediatek,mt8192-apmixedsys" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_apmixed);
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static int clk_mt8192_apmixed_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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const u8 *fhctl_node = "mediatek,mt8192-fhctl";
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int r;
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clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
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if (!clk_data)
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return -ENOMEM;
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fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
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r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
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pllfhs, ARRAY_SIZE(pllfhs), clk_data);
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if (r)
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goto free_clk_data;
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r = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
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ARRAY_SIZE(apmixed_clks), clk_data);
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if (r)
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goto unregister_plls;
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (r)
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goto unregister_gates;
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return r;
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unregister_gates:
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mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
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unregister_plls:
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mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
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ARRAY_SIZE(pllfhs), clk_data);
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free_clk_data:
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mtk_free_clk_data(clk_data);
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return r;
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}
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static void clk_mt8192_apmixed_remove(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
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of_clk_del_provider(node);
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mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
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mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
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ARRAY_SIZE(pllfhs), clk_data);
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mtk_free_clk_data(clk_data);
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}
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static struct platform_driver clk_mt8192_apmixed_drv = {
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.driver = {
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.name = "clk-mt8192-apmixed",
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.of_match_table = of_match_clk_mt8192_apmixed,
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},
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.probe = clk_mt8192_apmixed_probe,
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.remove_new = clk_mt8192_apmixed_remove,
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};
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module_platform_driver(clk_mt8192_apmixed_drv);
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MODULE_DESCRIPTION("MediaTek MT8192 apmixed clocks driver");
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MODULE_LICENSE("GPL");
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