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a65615df5b
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert all mediatek clk drivers from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230430190233.878921-4-u.kleine-koenig@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
233 lines
7.7 KiB
C
233 lines
7.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// Copyright (c) 2021 MediaTek Inc.
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// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
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#include "clk-fhctl.h"
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include "clk-pll.h"
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#include "clk-pllfh.h"
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#include <dt-bindings/clock/mt8195-clk.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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static const struct mtk_gate_regs apmixed_cg_regs = {
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.set_ofs = 0x8,
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.clr_ofs = 0x8,
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.sta_ofs = 0x8,
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};
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#define GATE_APMIXED(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
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static const struct mtk_gate apmixed_clks[] = {
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GATE_APMIXED(CLK_APMIXED_PLL_SSUSB26M, "pll_ssusb26m", "clk26m", 1),
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};
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#define MT8195_PLL_FMAX (3800UL * MHZ)
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#define MT8195_PLL_FMIN (1500UL * MHZ)
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#define MT8195_INTEGER_BITS 8
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#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
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_rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
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_tuner_reg, _tuner_en_reg, _tuner_en_bit, \
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_pcw_reg, _pcw_shift, _pcw_chg_reg, \
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_en_reg, _pll_en_bit) { \
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.id = _id, \
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.name = _name, \
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.reg = _reg, \
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.pwr_reg = _pwr_reg, \
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.en_mask = _en_mask, \
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.flags = _flags, \
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.rst_bar_mask = _rst_bar_mask, \
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.fmax = MT8195_PLL_FMAX, \
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.fmin = MT8195_PLL_FMIN, \
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.pcwbits = _pcwbits, \
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.pcwibits = MT8195_INTEGER_BITS, \
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.pd_reg = _pd_reg, \
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.pd_shift = _pd_shift, \
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.tuner_reg = _tuner_reg, \
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.tuner_en_reg = _tuner_en_reg, \
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.tuner_en_bit = _tuner_en_bit, \
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.pcw_reg = _pcw_reg, \
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.pcw_shift = _pcw_shift, \
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.pcw_chg_reg = _pcw_chg_reg, \
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.en_reg = _en_reg, \
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.pll_en_bit = _pll_en_bit, \
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}
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static const struct mtk_pll_data plls[] = {
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PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x0390, 0x03a0, 0,
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0, 0, 22, 0x0398, 24, 0, 0, 0, 0x0398, 0, 0x0398, 0, 9),
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PLL(CLK_APMIXED_RESPLL, "respll", 0x0190, 0x0320, 0,
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0, 0, 22, 0x0198, 24, 0, 0, 0, 0x0198, 0, 0x0198, 0, 9),
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PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x0360, 0x0370, 0,
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0, 0, 22, 0x0368, 24, 0, 0, 0, 0x0368, 0, 0x0368, 0, 9),
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PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0710, 0x0720, 0,
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0, 0, 22, 0x0718, 24, 0, 0, 0, 0x0718, 0, 0x0718, 0, 9),
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PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x00a0, 0x00b0, 0,
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0, 0, 22, 0x00a8, 24, 0, 0, 0, 0x00a8, 0, 0x00a8, 0, 9),
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PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x00c0, 0x00d0, 0,
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0, 0, 22, 0x00c8, 24, 0, 0, 0, 0x00c8, 0, 0x00c8, 0, 9),
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PLL(CLK_APMIXED_MMPLL, "mmpll", 0x00e0, 0x00f0, 0xff000000,
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HAVE_RST_BAR, BIT(23), 22, 0x00e8, 24, 0, 0, 0, 0x00e8, 0, 0x00e8, 0, 9),
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PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x01d0, 0x01e0, 0xff000000,
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HAVE_RST_BAR, BIT(23), 22, 0x01d8, 24, 0, 0, 0, 0x01d8, 0, 0x01d8, 0, 9),
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PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x0890, 0x08a0, 0,
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0, 0, 22, 0x0898, 24, 0, 0, 0, 0x0898, 0, 0x0898, 0, 9),
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PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0100, 0x0110, 0,
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0, 0, 22, 0x0108, 24, 0, 0, 0, 0x0108, 0, 0x0108, 0, 9),
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PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x01f0, 0x0700, 0xff000000,
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HAVE_RST_BAR, BIT(23), 22, 0x01f8, 24, 0, 0, 0, 0x01f8, 0, 0x01f8, 0, 9),
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PLL(CLK_APMIXED_HDMIPLL1, "hdmipll1", 0x08c0, 0x08d0, 0,
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0, 0, 22, 0x08c8, 24, 0, 0, 0, 0x08c8, 0, 0x08c8, 0, 9),
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PLL(CLK_APMIXED_HDMIPLL2, "hdmipll2", 0x0870, 0x0880, 0,
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0, 0, 22, 0x0878, 24, 0, 0, 0, 0x0878, 0, 0x0878, 0, 9),
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PLL(CLK_APMIXED_HDMIRX_APLL, "hdmirx_apll", 0x08e0, 0x0dd4, 0,
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0, 0, 32, 0x08e8, 24, 0, 0, 0, 0x08ec, 0, 0x08e8, 0, 9),
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PLL(CLK_APMIXED_USB1PLL, "usb1pll", 0x01a0, 0x01b0, 0,
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0, 0, 22, 0x01a8, 24, 0, 0, 0, 0x01a8, 0, 0x01a8, 0, 9),
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PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x07e0, 0x07f0, 0,
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0, 0, 22, 0x07e8, 24, 0, 0, 0, 0x07e8, 0, 0x07e8, 0, 9),
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PLL(CLK_APMIXED_APLL1, "apll1", 0x07c0, 0x0dc0, 0,
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0, 0, 32, 0x07c8, 24, 0x0470, 0x0000, 12, 0x07cc, 0, 0x07c8, 0, 9),
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PLL(CLK_APMIXED_APLL2, "apll2", 0x0780, 0x0dc4, 0,
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0, 0, 32, 0x0788, 24, 0x0474, 0x0000, 13, 0x078c, 0, 0x0788, 0, 9),
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PLL(CLK_APMIXED_APLL3, "apll3", 0x0760, 0x0dc8, 0,
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0, 0, 32, 0x0768, 24, 0x0478, 0x0000, 14, 0x076c, 0, 0x0768, 0, 9),
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PLL(CLK_APMIXED_APLL4, "apll4", 0x0740, 0x0dcc, 0,
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0, 0, 32, 0x0748, 24, 0x047C, 0x0000, 15, 0x074c, 0, 0x0748, 0, 9),
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PLL(CLK_APMIXED_APLL5, "apll5", 0x07a0, 0x0dd0, 0x100000,
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0, 0, 32, 0x07a8, 24, 0x0480, 0x0000, 16, 0x07ac, 0, 0x07a8, 0, 9),
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PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0340, 0x0350, 0,
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0, 0, 22, 0x0348, 24, 0, 0, 0, 0x0348, 0, 0x0348, 0, 9),
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PLL(CLK_APMIXED_DGIPLL, "dgipll", 0x0150, 0x0160, 0,
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0, 0, 22, 0x0158, 24, 0, 0, 0, 0x0158, 0, 0x0158, 0, 9),
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};
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enum fh_pll_id {
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FH_ARMPLL_LL,
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FH_ARMPLL_BL,
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FH_MEMPLL,
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FH_ADSPPLL,
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FH_NNAPLL,
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FH_CCIPLL,
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FH_MFGPLL,
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FH_TVDPLL2,
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FH_MPLL,
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FH_MMPLL,
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FH_MAINPLL,
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FH_MSDCPLL,
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FH_IMGPLL,
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FH_VDECPLL,
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FH_TVDPLL1,
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FH_NR_FH,
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};
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#define FH(_pllid, _fhid, _offset) { \
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.data = { \
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.pll_id = _pllid, \
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.fh_id = _fhid, \
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.fh_ver = FHCTL_PLLFH_V2, \
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.fhx_offset = _offset, \
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.dds_mask = GENMASK(21, 0), \
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.slope0_value = 0x6003c97, \
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.slope1_value = 0x6003c97, \
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.sfstrx_en = BIT(2), \
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.frddsx_en = BIT(1), \
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.fhctlx_en = BIT(0), \
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.tgl_org = BIT(31), \
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.dvfs_tri = BIT(31), \
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.pcwchg = BIT(31), \
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.dt_val = 0x0, \
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.df_val = 0x9, \
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.updnlmt_shft = 16, \
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.msk_frddsx_dys = GENMASK(23, 20), \
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.msk_frddsx_dts = GENMASK(19, 16), \
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}, \
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}
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static struct mtk_pllfh_data pllfhs[] = {
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FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x78),
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FH(CLK_APMIXED_NNAPLL, FH_NNAPLL, 0x8c),
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FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0xb4),
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FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL2, 0xc8),
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FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0),
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FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104),
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FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118),
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FH(CLK_APMIXED_IMGPLL, FH_IMGPLL, 0x12c),
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FH(CLK_APMIXED_VDECPLL, FH_VDECPLL, 0x140),
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FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL1, 0x154),
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};
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static const struct of_device_id of_match_clk_mt8195_apmixed[] = {
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{ .compatible = "mediatek,mt8195-apmixedsys", },
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{}
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_apmixed);
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static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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const u8 *fhctl_node = "mediatek,mt8195-fhctl";
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int r;
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clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
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if (!clk_data)
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return -ENOMEM;
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fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
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r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
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pllfhs, ARRAY_SIZE(pllfhs), clk_data);
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if (r)
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goto free_apmixed_data;
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r = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
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ARRAY_SIZE(apmixed_clks), clk_data);
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if (r)
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goto unregister_plls;
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (r)
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goto unregister_gates;
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platform_set_drvdata(pdev, clk_data);
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return r;
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unregister_gates:
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mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
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unregister_plls:
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mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
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ARRAY_SIZE(pllfhs), clk_data);
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free_apmixed_data:
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mtk_free_clk_data(clk_data);
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return r;
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}
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static void clk_mt8195_apmixed_remove(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
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of_clk_del_provider(node);
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mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
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mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
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ARRAY_SIZE(pllfhs), clk_data);
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mtk_free_clk_data(clk_data);
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}
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static struct platform_driver clk_mt8195_apmixed_drv = {
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.probe = clk_mt8195_apmixed_probe,
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.remove_new = clk_mt8195_apmixed_remove,
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.driver = {
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.name = "clk-mt8195-apmixed",
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.of_match_table = of_match_clk_mt8195_apmixed,
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},
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};
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module_platform_driver(clk_mt8195_apmixed_drv);
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MODULE_LICENSE("GPL");
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