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8da312d657
The Frequency Hopping Controller (FHCTL) seems to have different versions, as it has a slightly different register layout on some older SoCs like MT6795, MT8173, MT8183 (and others). This driver is indeed compatible with at least some of those older IP revisions, so all we need to do is to add a way to select the right register layout at registration time. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230206100105.861720-2-angelogioacchino.delregno@collabora.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
83 lines
1.8 KiB
C
83 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Edward-JW Yang <edward-jw.yang@mediatek.com>
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*/
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#ifndef __CLK_PLLFH_H
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#define __CLK_PLLFH_H
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#include "clk-pll.h"
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struct fh_pll_state {
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void __iomem *base;
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u32 fh_enable;
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u32 ssc_rate;
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};
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struct fh_pll_data {
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int pll_id;
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int fh_id;
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int fh_ver;
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u32 fhx_offset;
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u32 dds_mask;
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u32 slope0_value;
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u32 slope1_value;
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u32 sfstrx_en;
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u32 frddsx_en;
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u32 fhctlx_en;
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u32 tgl_org;
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u32 dvfs_tri;
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u32 pcwchg;
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u32 dt_val;
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u32 df_val;
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u32 updnlmt_shft;
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u32 msk_frddsx_dys;
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u32 msk_frddsx_dts;
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};
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struct mtk_pllfh_data {
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struct fh_pll_state state;
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const struct fh_pll_data data;
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};
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struct fh_pll_regs {
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void __iomem *reg_hp_en;
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void __iomem *reg_clk_con;
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void __iomem *reg_rst_con;
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void __iomem *reg_slope0;
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void __iomem *reg_slope1;
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void __iomem *reg_cfg;
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void __iomem *reg_updnlmt;
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void __iomem *reg_dds;
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void __iomem *reg_dvfs;
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void __iomem *reg_mon;
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};
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struct mtk_fh {
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struct mtk_clk_pll clk_pll;
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struct fh_pll_regs regs;
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struct mtk_pllfh_data *pllfh_data;
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const struct fh_operation *ops;
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spinlock_t *lock;
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};
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struct fh_operation {
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int (*hopping)(struct mtk_fh *fh, unsigned int new_dds,
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unsigned int postdiv);
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int (*ssc_enable)(struct mtk_fh *fh, u32 rate);
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};
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int mtk_clk_register_pllfhs(struct device_node *node,
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const struct mtk_pll_data *plls, int num_plls,
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struct mtk_pllfh_data *pllfhs, int num_pllfhs,
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struct clk_hw_onecell_data *clk_data);
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void mtk_clk_unregister_pllfhs(const struct mtk_pll_data *plls, int num_plls,
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struct mtk_pllfh_data *pllfhs, int num_fhs,
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struct clk_hw_onecell_data *clk_data);
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void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllfhs,
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int num_pllfhs);
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#endif /* __CLK_PLLFH_H */
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