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a0bc8ae5a0
The infra_ao reset is needed for MT8192 and MT8195. - Add mtk_clk_rst_desc for MT8192 and MT8195 - Add register reset controller function for MT8192 infra_ao. - Move definition of infra reset from cl-mt8183.c to reset.h because it's the same definition with MT8192 and MT8195. - Add new definition of infra reset_4 for MT8192 and MT8195. - Add infra_ao_idx_map for MT8192 and MT8195. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> [Nícolas: Test for MT8192] Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-15-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
82 lines
2.5 KiB
C
82 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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*/
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#ifndef __DRV_CLK_MTK_RESET_H
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#define __DRV_CLK_MTK_RESET_H
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#include <linux/reset-controller.h>
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#include <linux/types.h>
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#define RST_NR_PER_BANK 32
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/* Infra global controller reset set register */
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#define INFRA_RST0_SET_OFFSET 0x120
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#define INFRA_RST1_SET_OFFSET 0x130
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#define INFRA_RST2_SET_OFFSET 0x140
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#define INFRA_RST3_SET_OFFSET 0x150
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#define INFRA_RST4_SET_OFFSET 0x730
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/**
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* enum mtk_reset_version - Version of MediaTek clock reset controller.
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* @MTK_RST_SIMPLE: Use the same registers for bit set and clear.
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* @MTK_RST_SET_CLR: Use separate registers for bit set and clear.
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* @MTK_RST_MAX: Total quantity of version for MediaTek clock reset controller.
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*/
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enum mtk_reset_version {
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MTK_RST_SIMPLE = 0,
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MTK_RST_SET_CLR,
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MTK_RST_MAX,
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};
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/**
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* struct mtk_clk_rst_desc - Description of MediaTek clock reset.
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* @version: Reset version which is defined in enum mtk_reset_version.
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* @rst_bank_ofs: Pointer to an array containing base offsets of the reset register.
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* @rst_bank_nr: Quantity of reset bank.
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* @rst_idx_map:Pointer to an array containing ids if input argument is index.
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* This array is not necessary if our input argument does not mean index.
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* @rst_idx_map_nr: Quantity of reset index map.
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*/
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struct mtk_clk_rst_desc {
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enum mtk_reset_version version;
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u16 *rst_bank_ofs;
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u32 rst_bank_nr;
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u16 *rst_idx_map;
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u32 rst_idx_map_nr;
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};
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/**
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* struct mtk_clk_rst_data - Data of MediaTek clock reset controller.
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* @regmap: Pointer to base address of reset register address.
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* @rcdev: Reset controller device.
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* @desc: Pointer to description of the reset controller.
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*/
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struct mtk_clk_rst_data {
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struct regmap *regmap;
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struct reset_controller_dev rcdev;
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const struct mtk_clk_rst_desc *desc;
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};
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/**
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* mtk_register_reset_controller - Register MediaTek clock reset controller
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* @np: Pointer to device node.
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* @desc: Constant pointer to description of clock reset.
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*
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* Return: 0 on success and errorno otherwise.
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*/
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int mtk_register_reset_controller(struct device_node *np,
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const struct mtk_clk_rst_desc *desc);
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/**
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* mtk_register_reset_controller - Register mediatek clock reset controller with device
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* @np: Pointer to device.
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* @desc: Constant pointer to description of clock reset.
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*
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* Return: 0 on success and errorno otherwise.
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*/
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int mtk_register_reset_controller_with_dev(struct device *dev,
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const struct mtk_clk_rst_desc *desc);
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#endif /* __DRV_CLK_MTK_RESET_H */
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