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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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9bbcb892a7
The GPU_CC block on SC8280XP is powered by the GFX rail. We need to ensure that it's enabled to prevent unwanted power collapse. Enable runtime PM to keep the power flowing only when necessary. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230619-topic-sc8280xp-clk-rpm-v1-1-1e5e1064cdb2@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
476 lines
12 KiB
C
476 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk-provider.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap-divider.h"
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#include "common.h"
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#include "reset.h"
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#include "gdsc.h"
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/* Need to match the order of clocks in DT binding */
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enum {
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DT_BI_TCXO,
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DT_GCC_GPU_GPLL0_CLK_SRC,
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DT_GCC_GPU_GPLL0_DIV_CLK_SRC,
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};
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enum {
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P_BI_TCXO,
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P_GCC_GPU_GPLL0_CLK_SRC,
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P_GCC_GPU_GPLL0_DIV_CLK_SRC,
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P_GPU_CC_PLL0_OUT_MAIN,
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P_GPU_CC_PLL1_OUT_MAIN,
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};
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static const struct clk_parent_data parent_data_tcxo = { .index = DT_BI_TCXO };
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static const struct pll_vco lucid_5lpe_vco[] = {
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{ 249600000, 1800000000, 0 },
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};
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static struct alpha_pll_config gpu_cc_pll0_config = {
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.l = 0x1c,
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.alpha = 0xa555,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00002261,
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.config_ctl_hi1_val = 0x2a9a699c,
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.test_ctl_val = 0x00000000,
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.test_ctl_hi_val = 0x00000000,
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.test_ctl_hi1_val = 0x01800000,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00000805,
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.user_ctl_hi1_val = 0x00000000,
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};
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static struct clk_alpha_pll gpu_cc_pll0 = {
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.offset = 0x0,
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.vco_table = lucid_5lpe_vco,
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.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
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.clkr = {
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_pll0",
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.parent_data = &parent_data_tcxo,
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_5lpe_ops,
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},
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},
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};
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static struct alpha_pll_config gpu_cc_pll1_config = {
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.l = 0x1A,
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.alpha = 0xaaa,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00002261,
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.config_ctl_hi1_val = 0x2a9a699c,
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.test_ctl_val = 0x00000000,
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.test_ctl_hi_val = 0x00000000,
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.test_ctl_hi1_val = 0x01800000,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00000805,
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.user_ctl_hi1_val = 0x00000000,
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};
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static struct clk_alpha_pll gpu_cc_pll1 = {
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.offset = 0x100,
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.vco_table = lucid_5lpe_vco,
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.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
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.clkr = {
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_pll1",
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.parent_data = &parent_data_tcxo,
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_5lpe_ops,
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},
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},
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};
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static const struct parent_map gpu_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
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{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
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{ P_GCC_GPU_GPLL0_CLK_SRC, 5 },
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{ P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 },
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};
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static const struct clk_parent_data gpu_cc_parent_data_0[] = {
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{ .index = DT_BI_TCXO },
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{ .hw = &gpu_cc_pll0.clkr.hw },
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{ .hw = &gpu_cc_pll1.clkr.hw },
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{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
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{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
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};
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static const struct parent_map gpu_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
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{ P_GCC_GPU_GPLL0_CLK_SRC, 5 },
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{ P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 },
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};
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static const struct clk_parent_data gpu_cc_parent_data_1[] = {
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{ .index = DT_BI_TCXO },
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{ .hw = &gpu_cc_pll1.clkr.hw },
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{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
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{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
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};
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static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(200000000, P_GCC_GPU_GPLL0_DIV_CLK_SRC, 1.5, 0, 0),
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F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 gpu_cc_gmu_clk_src = {
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.cmd_rcgr = 0x1120,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_cc_parent_map_0,
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.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_gmu_clk_src",
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.parent_data = gpu_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
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F(200000000, P_GCC_GPU_GPLL0_CLK_SRC, 3, 0, 0),
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F(300000000, P_GCC_GPU_GPLL0_CLK_SRC, 2, 0, 0),
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F(400000000, P_GCC_GPU_GPLL0_CLK_SRC, 1.5, 0, 0),
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{ }
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};
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static struct clk_rcg2 gpu_cc_hub_clk_src = {
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.cmd_rcgr = 0x117c,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_cc_parent_map_1,
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.freq_tbl = ftbl_gpu_cc_hub_clk_src,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_hub_clk_src",
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.parent_data = gpu_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
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.reg = 0x11c0,
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.shift = 0,
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.width = 4,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "gpu_cc_hub_ahb_div_clk_src",
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.parent_hws = (const struct clk_hw*[]){
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&gpu_cc_hub_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_regmap_div_ro_ops,
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},
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};
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static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = {
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.reg = 0x11bc,
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.shift = 0,
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.width = 4,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "gpu_cc_hub_cx_int_div_clk_src",
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.parent_hws = (const struct clk_hw*[]){
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&gpu_cc_hub_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_regmap_div_ro_ops,
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},
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};
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static struct clk_branch gpu_cc_ahb_clk = {
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.halt_reg = 0x1078,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1078,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_ahb_clk",
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.parent_hws = (const struct clk_hw*[]){
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&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_crc_ahb_clk = {
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.halt_reg = 0x107c,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x107c,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_crc_ahb_clk",
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.parent_hws = (const struct clk_hw*[]){
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&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_gmu_clk = {
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.halt_reg = 0x1098,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1098,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_cx_gmu_clk",
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.parent_hws = (const struct clk_hw*[]){
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&gpu_cc_gmu_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_aon_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
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.halt_reg = 0x108c,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x108c,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_cx_snoc_dvm_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cxo_aon_clk = {
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.halt_reg = 0x1004,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x1004,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_cxo_aon_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_gx_gmu_clk = {
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.halt_reg = 0x1064,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1064,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_gx_gmu_clk",
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.parent_hws = (const struct clk_hw*[]){
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&gpu_cc_gmu_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
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.halt_reg = 0x5000,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x5000,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_hub_aon_clk = {
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.halt_reg = 0x1178,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1178,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_hub_aon_clk",
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.parent_hws = (const struct clk_hw*[]){
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&gpu_cc_hub_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_aon_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_hub_cx_int_clk = {
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.halt_reg = 0x1204,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1204,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_hub_cx_int_clk",
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.parent_hws = (const struct clk_hw*[]){
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&gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_aon_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_sleep_clk = {
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.halt_reg = 0x1090,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x1090,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_sleep_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_regmap *gpu_cc_sc8280xp_clocks[] = {
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[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
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[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
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[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
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[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
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[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
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[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
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[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
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[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
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[GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
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[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
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[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
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[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
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[GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr,
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[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
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[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
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[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
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};
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static struct gdsc cx_gdsc = {
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.gdscr = 0x106c,
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.gds_hw_ctrl = 0x1540,
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.pd = {
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.name = "cx_gdsc",
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},
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.pwrsts = PWRSTS_OFF_ON,
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.flags = VOTABLE | RETAIN_FF_ENABLE,
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};
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static struct gdsc gx_gdsc = {
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.gdscr = 0x100c,
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.clamp_io_ctrl = 0x1508,
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.pd = {
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.name = "gx_gdsc",
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.power_on = gdsc_gx_do_nothing_enable,
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},
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.pwrsts = PWRSTS_OFF_ON,
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.flags = CLAMP_IO | RETAIN_FF_ENABLE,
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};
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static struct gdsc *gpu_cc_sc8280xp_gdscs[] = {
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[GPU_CC_CX_GDSC] = &cx_gdsc,
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[GPU_CC_GX_GDSC] = &gx_gdsc,
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};
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static const struct regmap_config gpu_cc_sc8280xp_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x8030,
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.fast_io = true,
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};
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static struct qcom_cc_desc gpu_cc_sc8280xp_desc = {
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.config = &gpu_cc_sc8280xp_regmap_config,
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.clks = gpu_cc_sc8280xp_clocks,
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.num_clks = ARRAY_SIZE(gpu_cc_sc8280xp_clocks),
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.gdscs = gpu_cc_sc8280xp_gdscs,
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.num_gdscs = ARRAY_SIZE(gpu_cc_sc8280xp_gdscs),
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};
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static int gpu_cc_sc8280xp_probe(struct platform_device *pdev)
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{
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struct regmap *regmap;
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int ret;
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ret = devm_pm_runtime_enable(&pdev->dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = pm_runtime_resume_and_get(&pdev->dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
regmap = qcom_cc_map(pdev, &gpu_cc_sc8280xp_desc);
|
|
if (IS_ERR(regmap)) {
|
|
pm_runtime_put(&pdev->dev);
|
|
return PTR_ERR(regmap);
|
|
}
|
|
|
|
clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
|
|
clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
|
|
|
|
/*
|
|
* Keep the clocks always-ON
|
|
* GPU_CC_CB_CLK, GPU_CC_CXO_CLK
|
|
*/
|
|
regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0));
|
|
regmap_update_bits(regmap, 0x109c, BIT(0), BIT(0));
|
|
|
|
ret = qcom_cc_really_probe(pdev, &gpu_cc_sc8280xp_desc, regmap);
|
|
pm_runtime_put(&pdev->dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct of_device_id gpu_cc_sc8280xp_match_table[] = {
|
|
{ .compatible = "qcom,sc8280xp-gpucc" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, gpu_cc_sc8280xp_match_table);
|
|
|
|
static struct platform_driver gpu_cc_sc8280xp_driver = {
|
|
.probe = gpu_cc_sc8280xp_probe,
|
|
.driver = {
|
|
.name = "gpu_cc-sc8280xp",
|
|
.of_match_table = gpu_cc_sc8280xp_match_table,
|
|
},
|
|
};
|
|
module_platform_driver(gpu_cc_sc8280xp_driver);
|
|
|
|
MODULE_DESCRIPTION("Qualcomm SC8280XP GPU clock controller");
|
|
MODULE_LICENSE("GPL");
|