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![Maxime Ripard](/assets/img/avatar_default.png)
The SoCFGPA gate clock implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidates to trigger that parent change are either the assigned-clock-parents device tree property or a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. Similarly, it doesn't look like the device tree using that clock driver uses any of the assigned-clock properties on that clock. So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent(). The latter case would be equivalent to setting the determine_rate implementation to clk_hw_determine_rate_no_reparent(). Indeed, if no determine_rate implementation is provided, clk_round_rate() (through clk_core_round_rate_nolock()) will call itself on the parent if CLK_SET_RATE_PARENT is set, and will not change the clock rate otherwise. And if it was an oversight, then we are at least explicit about our behavior now and it can be further refined down the line. Cc: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-32-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
204 lines
5.1 KiB
C
204 lines
5.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2011-2012 Calxeda, Inc.
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* Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
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*
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* Based from clk-highbank.c
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*/
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#include <linux/slab.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include "clk.h"
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#define SOCFPGA_L4_MP_CLK "l4_mp_clk"
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#define SOCFPGA_L4_SP_CLK "l4_sp_clk"
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#define SOCFPGA_NAND_CLK "nand_clk"
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#define SOCFPGA_NAND_X_CLK "nand_x_clk"
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#define SOCFPGA_MMC_CLK "sdmmc_clk"
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#define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8
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#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
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/* SDMMC Group for System Manager defines */
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#define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108
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static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
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{
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u32 l4_src;
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u32 perpll_src;
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const char *name = clk_hw_get_name(hwclk);
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if (streq(name, SOCFPGA_L4_MP_CLK)) {
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l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
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return l4_src & 0x1;
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}
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if (streq(name, SOCFPGA_L4_SP_CLK)) {
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l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
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return !!(l4_src & 2);
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}
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perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
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if (streq(name, SOCFPGA_MMC_CLK))
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return perpll_src & 0x3;
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if (streq(name, SOCFPGA_NAND_CLK) ||
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streq(name, SOCFPGA_NAND_X_CLK))
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return (perpll_src >> 2) & 3;
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/* QSPI clock */
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return (perpll_src >> 4) & 3;
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}
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static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
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{
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u32 src_reg;
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const char *name = clk_hw_get_name(hwclk);
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if (streq(name, SOCFPGA_L4_MP_CLK)) {
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src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
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src_reg &= ~0x1;
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src_reg |= parent;
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writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
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} else if (streq(name, SOCFPGA_L4_SP_CLK)) {
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src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
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src_reg &= ~0x2;
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src_reg |= (parent << 1);
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writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
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} else {
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src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
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if (streq(name, SOCFPGA_MMC_CLK)) {
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src_reg &= ~0x3;
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src_reg |= parent;
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} else if (streq(name, SOCFPGA_NAND_CLK) ||
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streq(name, SOCFPGA_NAND_X_CLK)) {
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src_reg &= ~0xC;
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src_reg |= (parent << 2);
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} else {/* QSPI clock */
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src_reg &= ~0x30;
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src_reg |= (parent << 4);
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}
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writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
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}
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return 0;
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}
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static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
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u32 div = 1, val;
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if (socfpgaclk->fixed_div)
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div = socfpgaclk->fixed_div;
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else if (socfpgaclk->div_reg) {
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val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
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val &= GENMASK(socfpgaclk->width - 1, 0);
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/* Check for GPIO_DB_CLK by its offset */
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if ((uintptr_t) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
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div = val + 1;
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else
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div = (1 << val);
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}
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return parent_rate / div;
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}
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static struct clk_ops gateclk_ops = {
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.recalc_rate = socfpga_clk_recalc_rate,
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.determine_rate = clk_hw_determine_rate_no_reparent,
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.get_parent = socfpga_clk_get_parent,
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.set_parent = socfpga_clk_set_parent,
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};
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void __init socfpga_gate_init(struct device_node *node)
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{
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u32 clk_gate[2];
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u32 div_reg[3];
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u32 fixed_div;
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struct clk_hw *hw_clk;
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struct socfpga_gate_clk *socfpga_clk;
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const char *clk_name = node->name;
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const char *parent_name[SOCFPGA_MAX_PARENTS];
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struct clk_init_data init;
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struct clk_ops *ops;
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int rc;
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socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
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if (WARN_ON(!socfpga_clk))
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return;
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ops = kmemdup(&gateclk_ops, sizeof(gateclk_ops), GFP_KERNEL);
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if (WARN_ON(!ops))
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goto err_kmemdup;
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rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
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if (rc)
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clk_gate[0] = 0;
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if (clk_gate[0]) {
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socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
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socfpga_clk->hw.bit_idx = clk_gate[1];
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ops->enable = clk_gate_ops.enable;
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ops->disable = clk_gate_ops.disable;
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}
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rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
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if (rc)
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socfpga_clk->fixed_div = 0;
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else
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socfpga_clk->fixed_div = fixed_div;
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rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
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if (!rc) {
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socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
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socfpga_clk->shift = div_reg[1];
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socfpga_clk->width = div_reg[2];
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} else {
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socfpga_clk->div_reg = NULL;
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}
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of_property_read_string(node, "clock-output-names", &clk_name);
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init.name = clk_name;
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init.ops = ops;
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init.flags = 0;
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init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
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if (init.num_parents < 2) {
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ops->get_parent = NULL;
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ops->set_parent = NULL;
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}
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init.parent_names = parent_name;
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socfpga_clk->hw.hw.init = &init;
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hw_clk = &socfpga_clk->hw.hw;
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rc = clk_hw_register(NULL, hw_clk);
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if (rc) {
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pr_err("Could not register clock:%s\n", clk_name);
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goto err_clk_hw_register;
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}
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rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw_clk);
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if (rc) {
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pr_err("Could not register clock provider for node:%s\n",
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clk_name);
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goto err_of_clk_add_hw_provider;
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}
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return;
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err_of_clk_add_hw_provider:
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clk_hw_unregister(hw_clk);
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err_clk_hw_register:
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kfree(ops);
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err_kmemdup:
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kfree(socfpga_clk);
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}
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