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![Dario Binacchi](/assets/img/avatar_default.png)
The ti_clk_register() and ti_clk_register_omap_hw() functions are always called with the parameter of type "struct device" set to NULL, since the functions from which they are called always have a parameter of type "struct device_node". Replacing "struct device" type parameter with "struct device_node" will allow you to register a TI clock to the common clock framework by taking advantage of the facilities provided by the "struct device_node" type. Further, adding the "of_" prefix to the name of these functions explicitly binds them to the "struct device_node" type. The patch has been tested on a Beaglebone board. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Tested-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20221113181147.1626585-1-dario.binacchi@amarulasolutions.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
567 lines
12 KiB
C
567 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* TI Divider Clock
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* Tero Kristo <t-kristo@ti.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/clk/ti.h>
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#include "clock.h"
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#undef pr_fmt
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#define pr_fmt(fmt) "%s: " fmt, __func__
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static unsigned int _get_table_div(const struct clk_div_table *table,
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unsigned int val)
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{
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->val == val)
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return clkt->div;
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return 0;
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}
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static void _setup_mask(struct clk_omap_divider *divider)
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{
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u16 mask;
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u32 max_val;
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const struct clk_div_table *clkt;
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if (divider->table) {
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max_val = 0;
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for (clkt = divider->table; clkt->div; clkt++)
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if (clkt->val > max_val)
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max_val = clkt->val;
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} else {
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max_val = divider->max;
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if (!(divider->flags & CLK_DIVIDER_ONE_BASED) &&
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!(divider->flags & CLK_DIVIDER_POWER_OF_TWO))
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max_val--;
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}
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if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
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mask = fls(max_val) - 1;
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else
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mask = max_val;
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divider->mask = (1 << fls(mask)) - 1;
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}
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static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val)
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{
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if (divider->flags & CLK_DIVIDER_ONE_BASED)
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return val;
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if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
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return 1 << val;
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if (divider->table)
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return _get_table_div(divider->table, val);
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return val + 1;
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}
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static unsigned int _get_table_val(const struct clk_div_table *table,
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unsigned int div)
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{
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->div == div)
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return clkt->val;
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return 0;
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}
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static unsigned int _get_val(struct clk_omap_divider *divider, u8 div)
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{
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if (divider->flags & CLK_DIVIDER_ONE_BASED)
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return div;
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if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
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return __ffs(div);
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if (divider->table)
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return _get_table_val(divider->table, div);
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return div - 1;
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}
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static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_omap_divider *divider = to_clk_omap_divider(hw);
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unsigned int div, val;
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val = ti_clk_ll_ops->clk_readl(÷r->reg) >> divider->shift;
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val &= divider->mask;
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div = _get_div(divider, val);
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if (!div) {
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WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
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"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
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clk_hw_get_name(hw));
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return parent_rate;
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}
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return DIV_ROUND_UP(parent_rate, div);
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}
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/*
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* The reverse of DIV_ROUND_UP: The maximum number which
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* divided by m is r
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*/
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#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
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static bool _is_valid_table_div(const struct clk_div_table *table,
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unsigned int div)
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{
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->div == div)
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return true;
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return false;
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}
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static bool _is_valid_div(struct clk_omap_divider *divider, unsigned int div)
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{
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if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
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return is_power_of_2(div);
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if (divider->table)
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return _is_valid_table_div(divider->table, div);
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return true;
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}
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static int _div_round_up(const struct clk_div_table *table,
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unsigned long parent_rate, unsigned long rate)
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{
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const struct clk_div_table *clkt;
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int up = INT_MAX;
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int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
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for (clkt = table; clkt->div; clkt++) {
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if (clkt->div == div)
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return clkt->div;
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else if (clkt->div < div)
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continue;
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if ((clkt->div - div) < (up - div))
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up = clkt->div;
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}
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return up;
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}
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static int _div_round(const struct clk_div_table *table,
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unsigned long parent_rate, unsigned long rate)
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{
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if (!table)
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return DIV_ROUND_UP(parent_rate, rate);
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return _div_round_up(table, parent_rate, rate);
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}
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static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
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unsigned long *best_parent_rate)
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{
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struct clk_omap_divider *divider = to_clk_omap_divider(hw);
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int i, bestdiv = 0;
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unsigned long parent_rate, best = 0, now, maxdiv;
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unsigned long parent_rate_saved = *best_parent_rate;
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if (!rate)
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rate = 1;
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maxdiv = divider->max;
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if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
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parent_rate = *best_parent_rate;
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bestdiv = _div_round(divider->table, parent_rate, rate);
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bestdiv = bestdiv == 0 ? 1 : bestdiv;
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bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
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return bestdiv;
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}
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/*
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* The maximum divider we can use without overflowing
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* unsigned long in rate * i below
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*/
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maxdiv = min(ULONG_MAX / rate, maxdiv);
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for (i = 1; i <= maxdiv; i++) {
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if (!_is_valid_div(divider, i))
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continue;
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if (rate * i == parent_rate_saved) {
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/*
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* It's the most ideal case if the requested rate can be
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* divided from parent clock without needing to change
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* parent rate, so return the divider immediately.
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*/
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*best_parent_rate = parent_rate_saved;
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return i;
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}
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parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
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MULT_ROUND_UP(rate, i));
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now = DIV_ROUND_UP(parent_rate, i);
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if (now <= rate && now > best) {
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bestdiv = i;
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best = now;
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*best_parent_rate = parent_rate;
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}
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}
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if (!bestdiv) {
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bestdiv = divider->max;
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*best_parent_rate =
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clk_hw_round_rate(clk_hw_get_parent(hw), 1);
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}
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return bestdiv;
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}
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static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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int div;
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div = ti_clk_divider_bestdiv(hw, rate, prate);
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return DIV_ROUND_UP(*prate, div);
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}
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static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_omap_divider *divider;
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unsigned int div, value;
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u32 val;
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if (!hw || !rate)
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return -EINVAL;
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divider = to_clk_omap_divider(hw);
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div = DIV_ROUND_UP(parent_rate, rate);
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if (div > divider->max)
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div = divider->max;
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if (div < divider->min)
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div = divider->min;
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value = _get_val(divider, div);
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val = ti_clk_ll_ops->clk_readl(÷r->reg);
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val &= ~(divider->mask << divider->shift);
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val |= value << divider->shift;
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ti_clk_ll_ops->clk_writel(val, ÷r->reg);
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ti_clk_latch(÷r->reg, divider->latch);
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return 0;
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}
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/**
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* clk_divider_save_context - Save the divider value
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* @hw: pointer struct clk_hw
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*
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* Save the divider value
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*/
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static int clk_divider_save_context(struct clk_hw *hw)
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{
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struct clk_omap_divider *divider = to_clk_omap_divider(hw);
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u32 val;
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val = ti_clk_ll_ops->clk_readl(÷r->reg) >> divider->shift;
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divider->context = val & divider->mask;
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return 0;
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}
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/**
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* clk_divider_restore_context - restore the saved the divider value
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* @hw: pointer struct clk_hw
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*
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* Restore the saved the divider value
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*/
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static void clk_divider_restore_context(struct clk_hw *hw)
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{
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struct clk_omap_divider *divider = to_clk_omap_divider(hw);
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u32 val;
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val = ti_clk_ll_ops->clk_readl(÷r->reg);
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val &= ~(divider->mask << divider->shift);
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val |= divider->context << divider->shift;
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ti_clk_ll_ops->clk_writel(val, ÷r->reg);
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}
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const struct clk_ops ti_clk_divider_ops = {
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.recalc_rate = ti_clk_divider_recalc_rate,
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.round_rate = ti_clk_divider_round_rate,
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.set_rate = ti_clk_divider_set_rate,
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.save_context = clk_divider_save_context,
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.restore_context = clk_divider_restore_context,
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};
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static struct clk *_register_divider(struct device_node *node,
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u32 flags,
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struct clk_omap_divider *div)
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{
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struct clk *clk;
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struct clk_init_data init;
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const char *parent_name;
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const char *name;
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parent_name = of_clk_get_parent_name(node, 0);
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name = ti_dt_clk_name(node);
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init.name = name;
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init.ops = &ti_clk_divider_ops;
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init.flags = flags;
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init.parent_names = (parent_name ? &parent_name : NULL);
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init.num_parents = (parent_name ? 1 : 0);
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div->hw.init = &init;
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/* register the clock */
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clk = of_ti_clk_register(node, &div->hw, name);
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if (IS_ERR(clk))
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kfree(div);
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return clk;
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}
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int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
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u8 flags, struct clk_omap_divider *divider)
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{
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int valid_div = 0;
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int i;
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struct clk_div_table *tmp;
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u16 min_div = 0;
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if (!div_table) {
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divider->min = 1;
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divider->max = max_div;
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_setup_mask(divider);
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return 0;
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}
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i = 0;
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while (!num_dividers || i < num_dividers) {
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if (div_table[i] == -1)
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break;
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if (div_table[i])
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valid_div++;
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i++;
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}
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num_dividers = i;
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tmp = kcalloc(valid_div + 1, sizeof(*tmp), GFP_KERNEL);
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if (!tmp)
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return -ENOMEM;
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valid_div = 0;
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for (i = 0; i < num_dividers; i++)
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if (div_table[i] > 0) {
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tmp[valid_div].div = div_table[i];
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tmp[valid_div].val = i;
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valid_div++;
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if (div_table[i] > max_div)
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max_div = div_table[i];
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if (!min_div || div_table[i] < min_div)
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min_div = div_table[i];
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}
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divider->min = min_div;
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divider->max = max_div;
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divider->table = tmp;
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_setup_mask(divider);
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return 0;
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}
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static int __init ti_clk_get_div_table(struct device_node *node,
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struct clk_omap_divider *div)
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{
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struct clk_div_table *table;
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const __be32 *divspec;
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u32 val;
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u32 num_div;
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u32 valid_div;
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int i;
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divspec = of_get_property(node, "ti,dividers", &num_div);
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if (!divspec)
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return 0;
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num_div /= 4;
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valid_div = 0;
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/* Determine required size for divider table */
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for (i = 0; i < num_div; i++) {
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of_property_read_u32_index(node, "ti,dividers", i, &val);
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if (val)
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valid_div++;
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}
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if (!valid_div) {
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pr_err("no valid dividers for %pOFn table\n", node);
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return -EINVAL;
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}
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table = kcalloc(valid_div + 1, sizeof(*table), GFP_KERNEL);
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if (!table)
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return -ENOMEM;
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valid_div = 0;
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for (i = 0; i < num_div; i++) {
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of_property_read_u32_index(node, "ti,dividers", i, &val);
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if (val) {
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table[valid_div].div = val;
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table[valid_div].val = i;
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valid_div++;
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}
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}
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div->table = table;
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return 0;
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}
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static int _populate_divider_min_max(struct device_node *node,
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struct clk_omap_divider *divider)
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{
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u32 min_div = 0;
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u32 max_div = 0;
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u32 val;
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const struct clk_div_table *clkt;
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if (!divider->table) {
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/* Clk divider table not provided, determine min/max divs */
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if (of_property_read_u32(node, "ti,min-div", &min_div))
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min_div = 1;
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if (of_property_read_u32(node, "ti,max-div", &max_div)) {
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pr_err("no max-div for %pOFn!\n", node);
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return -EINVAL;
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}
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} else {
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for (clkt = divider->table; clkt->div; clkt++) {
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val = clkt->div;
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if (val > max_div)
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max_div = val;
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if (!min_div || val < min_div)
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min_div = val;
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}
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}
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divider->min = min_div;
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divider->max = max_div;
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_setup_mask(divider);
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return 0;
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}
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static int __init ti_clk_divider_populate(struct device_node *node,
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struct clk_omap_divider *div,
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u32 *flags)
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{
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u32 val;
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int ret;
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ret = ti_clk_get_reg_addr(node, 0, &div->reg);
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if (ret)
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return ret;
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if (!of_property_read_u32(node, "ti,bit-shift", &val))
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div->shift = val;
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else
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div->shift = 0;
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if (!of_property_read_u32(node, "ti,latch-bit", &val))
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div->latch = val;
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else
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div->latch = -EINVAL;
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*flags = 0;
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div->flags = 0;
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if (of_property_read_bool(node, "ti,index-starts-at-one"))
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div->flags |= CLK_DIVIDER_ONE_BASED;
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if (of_property_read_bool(node, "ti,index-power-of-two"))
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div->flags |= CLK_DIVIDER_POWER_OF_TWO;
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if (of_property_read_bool(node, "ti,set-rate-parent"))
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*flags |= CLK_SET_RATE_PARENT;
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ret = ti_clk_get_div_table(node, div);
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if (ret)
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return ret;
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return _populate_divider_min_max(node, div);
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}
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/**
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* of_ti_divider_clk_setup - Setup function for simple div rate clock
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* @node: device node for this clock
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*
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* Sets up a basic divider clock.
|
|
*/
|
|
static void __init of_ti_divider_clk_setup(struct device_node *node)
|
|
{
|
|
struct clk *clk;
|
|
u32 flags = 0;
|
|
struct clk_omap_divider *div;
|
|
|
|
div = kzalloc(sizeof(*div), GFP_KERNEL);
|
|
if (!div)
|
|
return;
|
|
|
|
if (ti_clk_divider_populate(node, div, &flags))
|
|
goto cleanup;
|
|
|
|
clk = _register_divider(node, flags, div);
|
|
if (!IS_ERR(clk)) {
|
|
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
|
of_ti_clk_autoidle_setup(node);
|
|
return;
|
|
}
|
|
|
|
cleanup:
|
|
kfree(div->table);
|
|
kfree(div);
|
|
}
|
|
CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup);
|
|
|
|
static void __init of_ti_composite_divider_clk_setup(struct device_node *node)
|
|
{
|
|
struct clk_omap_divider *div;
|
|
u32 tmp;
|
|
|
|
div = kzalloc(sizeof(*div), GFP_KERNEL);
|
|
if (!div)
|
|
return;
|
|
|
|
if (ti_clk_divider_populate(node, div, &tmp))
|
|
goto cleanup;
|
|
|
|
if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER))
|
|
return;
|
|
|
|
cleanup:
|
|
kfree(div->table);
|
|
kfree(div);
|
|
}
|
|
CLK_OF_DECLARE(ti_composite_divider_clk, "ti,composite-divider-clock",
|
|
of_ti_composite_divider_clk_setup);
|