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![Maxime Ripard](/assets/img/avatar_default.png)
The UX500 sysctrl "set_parent" clocks implement a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidates to trigger that parent change are either the assigned-clock-parents device tree property or a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. Similarly, it doesn't look like the device tree using that clock driver uses any of the assigned-clock properties on that clock. So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent(). The latter case would be equivalent to setting the determine_rate implementation to clk_hw_determine_rate_no_reparent(). Indeed, if no determine_rate implementation is provided, clk_round_rate() (through clk_core_round_rate_nolock()) will call itself on the parent if CLK_SET_RATE_PARENT is set, and will not change the clock rate otherwise. And if it was an oversight, then we are at least explicit about our behavior now and it can be further refined down the line. Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-38-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
226 lines
5.6 KiB
C
226 lines
5.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Sysctrl clock implementation for ux500 platform.
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*
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* Copyright (C) 2013 ST-Ericsson SA
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* Author: Ulf Hansson <ulf.hansson@linaro.org>
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*/
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#include <linux/clk-provider.h>
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#include <linux/mfd/abx500/ab8500-sysctrl.h>
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include "clk.h"
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#define SYSCTRL_MAX_NUM_PARENTS 4
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#define to_clk_sysctrl(_hw) container_of(_hw, struct clk_sysctrl, hw)
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struct clk_sysctrl {
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struct clk_hw hw;
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struct device *dev;
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u8 parent_index;
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u16 reg_sel[SYSCTRL_MAX_NUM_PARENTS];
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u8 reg_mask[SYSCTRL_MAX_NUM_PARENTS];
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u8 reg_bits[SYSCTRL_MAX_NUM_PARENTS];
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unsigned long rate;
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unsigned long enable_delay_us;
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};
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/* Sysctrl clock operations. */
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static int clk_sysctrl_prepare(struct clk_hw *hw)
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{
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int ret;
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struct clk_sysctrl *clk = to_clk_sysctrl(hw);
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ret = ab8500_sysctrl_write(clk->reg_sel[0], clk->reg_mask[0],
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clk->reg_bits[0]);
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if (!ret && clk->enable_delay_us)
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usleep_range(clk->enable_delay_us, clk->enable_delay_us +
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(clk->enable_delay_us >> 2));
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return ret;
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}
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static void clk_sysctrl_unprepare(struct clk_hw *hw)
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{
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struct clk_sysctrl *clk = to_clk_sysctrl(hw);
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if (ab8500_sysctrl_clear(clk->reg_sel[0], clk->reg_mask[0]))
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dev_err(clk->dev, "clk_sysctrl: %s fail to clear %s.\n",
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__func__, clk_hw_get_name(hw));
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}
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static unsigned long clk_sysctrl_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_sysctrl *clk = to_clk_sysctrl(hw);
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return clk->rate;
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}
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static int clk_sysctrl_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_sysctrl *clk = to_clk_sysctrl(hw);
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u8 old_index = clk->parent_index;
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int ret = 0;
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if (clk->reg_sel[old_index]) {
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ret = ab8500_sysctrl_clear(clk->reg_sel[old_index],
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clk->reg_mask[old_index]);
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if (ret)
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return ret;
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}
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if (clk->reg_sel[index]) {
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ret = ab8500_sysctrl_write(clk->reg_sel[index],
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clk->reg_mask[index],
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clk->reg_bits[index]);
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if (ret) {
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if (clk->reg_sel[old_index])
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ab8500_sysctrl_write(clk->reg_sel[old_index],
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clk->reg_mask[old_index],
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clk->reg_bits[old_index]);
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return ret;
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}
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}
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clk->parent_index = index;
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return ret;
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}
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static u8 clk_sysctrl_get_parent(struct clk_hw *hw)
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{
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struct clk_sysctrl *clk = to_clk_sysctrl(hw);
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return clk->parent_index;
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}
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static const struct clk_ops clk_sysctrl_gate_ops = {
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.prepare = clk_sysctrl_prepare,
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.unprepare = clk_sysctrl_unprepare,
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};
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static const struct clk_ops clk_sysctrl_gate_fixed_rate_ops = {
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.prepare = clk_sysctrl_prepare,
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.unprepare = clk_sysctrl_unprepare,
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.recalc_rate = clk_sysctrl_recalc_rate,
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};
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static const struct clk_ops clk_sysctrl_set_parent_ops = {
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.determine_rate = clk_hw_determine_rate_no_reparent,
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.set_parent = clk_sysctrl_set_parent,
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.get_parent = clk_sysctrl_get_parent,
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};
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static struct clk *clk_reg_sysctrl(struct device *dev,
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const char *name,
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const char **parent_names,
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u8 num_parents,
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u16 *reg_sel,
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u8 *reg_mask,
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u8 *reg_bits,
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unsigned long rate,
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unsigned long enable_delay_us,
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unsigned long flags,
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const struct clk_ops *clk_sysctrl_ops)
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{
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struct clk_sysctrl *clk;
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struct clk_init_data clk_sysctrl_init;
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struct clk *clk_reg;
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int i;
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if (!dev)
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return ERR_PTR(-EINVAL);
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if (!name || (num_parents > SYSCTRL_MAX_NUM_PARENTS)) {
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dev_err(dev, "clk_sysctrl: invalid arguments passed\n");
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return ERR_PTR(-EINVAL);
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}
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clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL);
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if (!clk)
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return ERR_PTR(-ENOMEM);
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/* set main clock registers */
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clk->reg_sel[0] = reg_sel[0];
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clk->reg_bits[0] = reg_bits[0];
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clk->reg_mask[0] = reg_mask[0];
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/* handle clocks with more than one parent */
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for (i = 1; i < num_parents; i++) {
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clk->reg_sel[i] = reg_sel[i];
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clk->reg_bits[i] = reg_bits[i];
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clk->reg_mask[i] = reg_mask[i];
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}
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clk->parent_index = 0;
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clk->rate = rate;
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clk->enable_delay_us = enable_delay_us;
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clk->dev = dev;
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clk_sysctrl_init.name = name;
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clk_sysctrl_init.ops = clk_sysctrl_ops;
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clk_sysctrl_init.flags = flags;
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clk_sysctrl_init.parent_names = parent_names;
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clk_sysctrl_init.num_parents = num_parents;
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clk->hw.init = &clk_sysctrl_init;
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clk_reg = devm_clk_register(clk->dev, &clk->hw);
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if (IS_ERR(clk_reg))
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dev_err(dev, "clk_sysctrl: clk_register failed\n");
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return clk_reg;
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}
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struct clk *clk_reg_sysctrl_gate(struct device *dev,
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const char *name,
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const char *parent_name,
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u16 reg_sel,
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u8 reg_mask,
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u8 reg_bits,
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unsigned long enable_delay_us,
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unsigned long flags)
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{
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const char **parent_names = (parent_name ? &parent_name : NULL);
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u8 num_parents = (parent_name ? 1 : 0);
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return clk_reg_sysctrl(dev, name, parent_names, num_parents,
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®_sel, ®_mask, ®_bits, 0, enable_delay_us,
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flags, &clk_sysctrl_gate_ops);
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}
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struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev,
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const char *name,
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const char *parent_name,
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u16 reg_sel,
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u8 reg_mask,
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u8 reg_bits,
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unsigned long rate,
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unsigned long enable_delay_us,
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unsigned long flags)
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{
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const char **parent_names = (parent_name ? &parent_name : NULL);
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u8 num_parents = (parent_name ? 1 : 0);
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return clk_reg_sysctrl(dev, name, parent_names, num_parents,
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®_sel, ®_mask, ®_bits,
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rate, enable_delay_us, flags,
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&clk_sysctrl_gate_fixed_rate_ops);
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}
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struct clk *clk_reg_sysctrl_set_parent(struct device *dev,
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const char *name,
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const char **parent_names,
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u8 num_parents,
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u16 *reg_sel,
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u8 *reg_mask,
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u8 *reg_bits,
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unsigned long flags)
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{
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return clk_reg_sysctrl(dev, name, parent_names, num_parents,
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reg_sel, reg_mask, reg_bits, 0, 0, flags,
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&clk_sysctrl_set_parent_ops);
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}
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