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![Xiu Jianfeng](/assets/img/avatar_default.png)
@pll->rate_table has allocated memory by kmemdup(), if clk_hw_register()
fails, it should be freed, otherwise it will cause memory leak issue,
this patch fixes it.
Fixes: b4cbe606dc
("clk: visconti: Add support common clock driver and reset driver")
Signed-off-by: Xiu Jianfeng <xiujianfeng@huawei.com>
Link: https://lore.kernel.org/r/20221122152353.204132-1-xiujianfeng@huawei.com
Acked-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
340 lines
8.6 KiB
C
340 lines
8.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Toshiba Visconti PLL driver
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*
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* Copyright (c) 2021 TOSHIBA CORPORATION
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* Copyright (c) 2021 Toshiba Electronic Devices & Storage Corporation
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*
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* Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include "pll.h"
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struct visconti_pll {
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struct clk_hw hw;
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void __iomem *pll_base;
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spinlock_t *lock;
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unsigned long flags;
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const struct visconti_pll_rate_table *rate_table;
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size_t rate_count;
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struct visconti_pll_provider *ctx;
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};
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#define PLL_CONF_REG 0x0000
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#define PLL_CTRL_REG 0x0004
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#define PLL_FRACMODE_REG 0x0010
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#define PLL_INTIN_REG 0x0014
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#define PLL_FRACIN_REG 0x0018
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#define PLL_REFDIV_REG 0x001c
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#define PLL_POSTDIV_REG 0x0020
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#define PLL_CONFIG_SEL BIT(0)
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#define PLL_PLLEN BIT(4)
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#define PLL_BYPASS BIT(16)
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#define PLL_INTIN_MASK GENMASK(11, 0)
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#define PLL_FRACIN_MASK GENMASK(23, 0)
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#define PLL_REFDIV_MASK GENMASK(5, 0)
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#define PLL_POSTDIV_MASK GENMASK(2, 0)
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#define PLL0_FRACMODE_DACEN BIT(4)
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#define PLL0_FRACMODE_DSMEN BIT(0)
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#define PLL_CREATE_FRACMODE(table) (table->dacen << 4 | table->dsmen)
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#define PLL_CREATE_OSTDIV(table) (table->postdiv2 << 4 | table->postdiv1)
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static inline struct visconti_pll *to_visconti_pll(struct clk_hw *hw)
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{
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return container_of(hw, struct visconti_pll, hw);
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}
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static void visconti_pll_get_params(struct visconti_pll *pll,
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struct visconti_pll_rate_table *rate_table)
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{
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u32 postdiv, val;
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val = readl(pll->pll_base + PLL_FRACMODE_REG);
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rate_table->dacen = FIELD_GET(PLL0_FRACMODE_DACEN, val);
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rate_table->dsmen = FIELD_GET(PLL0_FRACMODE_DSMEN, val);
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rate_table->fracin = readl(pll->pll_base + PLL_FRACIN_REG) & PLL_FRACIN_MASK;
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rate_table->intin = readl(pll->pll_base + PLL_INTIN_REG) & PLL_INTIN_MASK;
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rate_table->refdiv = readl(pll->pll_base + PLL_REFDIV_REG) & PLL_REFDIV_MASK;
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postdiv = readl(pll->pll_base + PLL_POSTDIV_REG);
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rate_table->postdiv1 = postdiv & PLL_POSTDIV_MASK;
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rate_table->postdiv2 = (postdiv >> 4) & PLL_POSTDIV_MASK;
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}
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static const struct visconti_pll_rate_table *visconti_get_pll_settings(struct visconti_pll *pll,
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unsigned long rate)
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{
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const struct visconti_pll_rate_table *rate_table = pll->rate_table;
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int i;
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for (i = 0; i < pll->rate_count; i++)
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if (rate == rate_table[i].rate)
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return &rate_table[i];
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return NULL;
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}
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static unsigned long visconti_get_pll_rate_from_data(struct visconti_pll *pll,
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const struct visconti_pll_rate_table *rate)
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{
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const struct visconti_pll_rate_table *rate_table = pll->rate_table;
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int i;
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for (i = 0; i < pll->rate_count; i++)
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if (memcmp(&rate_table[i].dacen, &rate->dacen,
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sizeof(*rate) - sizeof(unsigned long)) == 0)
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return rate_table[i].rate;
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/* set default */
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return rate_table[0].rate;
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}
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static long visconti_pll_round_rate(struct clk_hw *hw,
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unsigned long rate, unsigned long *prate)
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{
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struct visconti_pll *pll = to_visconti_pll(hw);
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const struct visconti_pll_rate_table *rate_table = pll->rate_table;
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int i;
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/* Assumming rate_table is in descending order */
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for (i = 0; i < pll->rate_count; i++)
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if (rate >= rate_table[i].rate)
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return rate_table[i].rate;
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/* return minimum supported value */
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return rate_table[i - 1].rate;
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}
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static unsigned long visconti_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct visconti_pll *pll = to_visconti_pll(hw);
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struct visconti_pll_rate_table rate_table;
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memset(&rate_table, 0, sizeof(rate_table));
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visconti_pll_get_params(pll, &rate_table);
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return visconti_get_pll_rate_from_data(pll, &rate_table);
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}
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static int visconti_pll_set_params(struct visconti_pll *pll,
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const struct visconti_pll_rate_table *rate_table)
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{
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writel(PLL_CREATE_FRACMODE(rate_table), pll->pll_base + PLL_FRACMODE_REG);
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writel(PLL_CREATE_OSTDIV(rate_table), pll->pll_base + PLL_POSTDIV_REG);
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writel(rate_table->intin, pll->pll_base + PLL_INTIN_REG);
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writel(rate_table->fracin, pll->pll_base + PLL_FRACIN_REG);
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writel(rate_table->refdiv, pll->pll_base + PLL_REFDIV_REG);
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return 0;
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}
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static int visconti_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct visconti_pll *pll = to_visconti_pll(hw);
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const struct visconti_pll_rate_table *rate_table;
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rate_table = visconti_get_pll_settings(pll, rate);
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if (!rate_table)
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return -EINVAL;
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return visconti_pll_set_params(pll, rate_table);
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}
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static int visconti_pll_is_enabled(struct clk_hw *hw)
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{
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struct visconti_pll *pll = to_visconti_pll(hw);
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u32 reg;
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reg = readl(pll->pll_base + PLL_CTRL_REG);
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return (reg & PLL_PLLEN);
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}
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static int visconti_pll_enable(struct clk_hw *hw)
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{
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struct visconti_pll *pll = to_visconti_pll(hw);
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const struct visconti_pll_rate_table *rate_table = pll->rate_table;
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unsigned long flags;
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u32 reg;
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if (visconti_pll_is_enabled(hw))
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return 0;
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spin_lock_irqsave(pll->lock, flags);
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writel(PLL_CONFIG_SEL, pll->pll_base + PLL_CONF_REG);
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reg = readl(pll->pll_base + PLL_CTRL_REG);
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reg |= PLL_BYPASS;
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writel(reg, pll->pll_base + PLL_CTRL_REG);
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visconti_pll_set_params(pll, &rate_table[0]);
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reg = readl(pll->pll_base + PLL_CTRL_REG);
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reg &= ~PLL_PLLEN;
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writel(reg, pll->pll_base + PLL_CTRL_REG);
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udelay(1);
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reg = readl(pll->pll_base + PLL_CTRL_REG);
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reg |= PLL_PLLEN;
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writel(reg, pll->pll_base + PLL_CTRL_REG);
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udelay(40);
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reg = readl(pll->pll_base + PLL_CTRL_REG);
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reg &= ~PLL_BYPASS;
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writel(reg, pll->pll_base + PLL_CTRL_REG);
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spin_unlock_irqrestore(pll->lock, flags);
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return 0;
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}
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static void visconti_pll_disable(struct clk_hw *hw)
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{
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struct visconti_pll *pll = to_visconti_pll(hw);
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unsigned long flags;
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u32 reg;
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if (!visconti_pll_is_enabled(hw))
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return;
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spin_lock_irqsave(pll->lock, flags);
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writel(PLL_CONFIG_SEL, pll->pll_base + PLL_CONF_REG);
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reg = readl(pll->pll_base + PLL_CTRL_REG);
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reg |= PLL_BYPASS;
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writel(reg, pll->pll_base + PLL_CTRL_REG);
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reg = readl(pll->pll_base + PLL_CTRL_REG);
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reg &= ~PLL_PLLEN;
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writel(reg, pll->pll_base + PLL_CTRL_REG);
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spin_unlock_irqrestore(pll->lock, flags);
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}
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static const struct clk_ops visconti_pll_ops = {
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.enable = visconti_pll_enable,
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.disable = visconti_pll_disable,
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.is_enabled = visconti_pll_is_enabled,
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.round_rate = visconti_pll_round_rate,
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.recalc_rate = visconti_pll_recalc_rate,
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.set_rate = visconti_pll_set_rate,
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};
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static struct clk_hw *visconti_register_pll(struct visconti_pll_provider *ctx,
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const char *name,
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const char *parent_name,
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int offset,
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const struct visconti_pll_rate_table *rate_table,
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spinlock_t *lock)
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{
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struct clk_init_data init;
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struct visconti_pll *pll;
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struct clk_hw *pll_hw_clk;
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size_t len;
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int ret;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.flags = CLK_IGNORE_UNUSED;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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for (len = 0; rate_table[len].rate != 0; )
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len++;
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pll->rate_count = len;
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pll->rate_table = kmemdup(rate_table,
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pll->rate_count * sizeof(struct visconti_pll_rate_table),
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GFP_KERNEL);
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WARN(!pll->rate_table, "%s: could not allocate rate table for %s\n", __func__, name);
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init.ops = &visconti_pll_ops;
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pll->hw.init = &init;
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pll->pll_base = ctx->reg_base + offset;
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pll->lock = lock;
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pll->ctx = ctx;
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pll_hw_clk = &pll->hw;
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ret = clk_hw_register(NULL, &pll->hw);
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if (ret) {
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pr_err("failed to register pll clock %s : %d\n", name, ret);
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kfree(pll->rate_table);
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kfree(pll);
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pll_hw_clk = ERR_PTR(ret);
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}
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return pll_hw_clk;
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}
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static void visconti_pll_add_lookup(struct visconti_pll_provider *ctx,
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struct clk_hw *hw_clk,
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unsigned int id)
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{
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if (id)
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ctx->clk_data.hws[id] = hw_clk;
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}
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void __init visconti_register_plls(struct visconti_pll_provider *ctx,
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const struct visconti_pll_info *list,
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unsigned int nr_plls,
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spinlock_t *lock)
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{
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int idx;
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for (idx = 0; idx < nr_plls; idx++, list++) {
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struct clk_hw *clk;
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clk = visconti_register_pll(ctx,
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list->name,
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list->parent,
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list->base_reg,
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list->rate_table,
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lock);
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if (IS_ERR(clk)) {
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pr_err("failed to register clock %s\n", list->name);
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continue;
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}
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visconti_pll_add_lookup(ctx, clk, list->id);
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}
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}
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struct visconti_pll_provider * __init visconti_init_pll(struct device_node *np,
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void __iomem *base,
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unsigned long nr_plls)
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{
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struct visconti_pll_provider *ctx;
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int i;
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ctx = kzalloc(struct_size(ctx, clk_data.hws, nr_plls), GFP_KERNEL);
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if (!ctx)
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return ERR_PTR(-ENOMEM);
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for (i = 0; i < nr_plls; ++i)
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ctx->clk_data.hws[i] = ERR_PTR(-ENOENT);
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ctx->node = np;
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ctx->reg_base = base;
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ctx->clk_data.num = nr_plls;
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return ctx;
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}
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