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106ef3bda2
One of the clock entry "dcl" clk has some HW limitations. One is that
its rate can only by changed by changing its parent clk's rate & two is
that HW does not support enable/disable for this clk.
Handle above two limitations by adding relevant flags. Add standard flag
CLK_SET_RATE_PARENT to handle rate change and add driver internal flag
DIV_CLK_NO_MASK to handle enable/disable.
Fixes: d058fd9e89 ("clk: intel: Add CGU clock driver for a new SoC")
Reviewed-by: Yi xin Zhu <yzhu@maxlinear.com>
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
Link: https://lore.kernel.org/r/a4770e7225f8a0c03c8ab2ba80434a4e8e9afb17.1665642720.git.rtanwar@maxlinear.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
335 lines
7.1 KiB
C
335 lines
7.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 MaxLinear, Inc.
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* Copyright (C) 2020 Intel Corporation.
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* Zhu Yixin <yzhu@maxlinear.com>
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* Rahul Tanwar <rtanwar@maxlinear.com>
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*/
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#ifndef __CLK_CGU_H
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#define __CLK_CGU_H
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#include <linux/regmap.h>
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struct lgm_clk_mux {
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struct clk_hw hw;
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struct regmap *membase;
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unsigned int reg;
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u8 shift;
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u8 width;
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unsigned long flags;
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};
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struct lgm_clk_divider {
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struct clk_hw hw;
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struct regmap *membase;
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unsigned int reg;
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u8 shift;
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u8 width;
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u8 shift_gate;
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u8 width_gate;
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unsigned long flags;
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const struct clk_div_table *table;
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};
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struct lgm_clk_ddiv {
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struct clk_hw hw;
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struct regmap *membase;
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unsigned int reg;
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u8 shift0;
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u8 width0;
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u8 shift1;
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u8 width1;
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u8 shift2;
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u8 width2;
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u8 shift_gate;
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u8 width_gate;
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unsigned int mult;
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unsigned int div;
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unsigned long flags;
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};
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struct lgm_clk_gate {
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struct clk_hw hw;
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struct regmap *membase;
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unsigned int reg;
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u8 shift;
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unsigned long flags;
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};
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enum lgm_clk_type {
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CLK_TYPE_FIXED,
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CLK_TYPE_MUX,
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CLK_TYPE_DIVIDER,
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CLK_TYPE_FIXED_FACTOR,
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CLK_TYPE_GATE,
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CLK_TYPE_NONE,
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};
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/**
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* struct lgm_clk_provider
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* @membase: IO mem base address for CGU.
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* @np: device node
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* @dev: device
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* @clk_data: array of hw clocks and clk number.
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*/
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struct lgm_clk_provider {
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struct regmap *membase;
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struct device_node *np;
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struct device *dev;
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struct clk_hw_onecell_data clk_data;
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};
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enum pll_type {
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TYPE_ROPLL,
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TYPE_LJPLL,
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TYPE_NONE,
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};
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struct lgm_clk_pll {
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struct clk_hw hw;
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struct regmap *membase;
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unsigned int reg;
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unsigned long flags;
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enum pll_type type;
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};
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/**
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* struct lgm_pll_clk_data
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* @id: platform specific id of the clock.
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* @name: name of this pll clock.
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* @parent_data: parent clock data.
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* @num_parents: number of parents.
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* @flags: optional flags for basic clock.
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* @type: platform type of pll.
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* @reg: offset of the register.
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*/
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struct lgm_pll_clk_data {
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unsigned int id;
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const char *name;
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const struct clk_parent_data *parent_data;
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u8 num_parents;
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unsigned long flags;
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enum pll_type type;
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int reg;
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};
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#define LGM_PLL(_id, _name, _pdata, _flags, \
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_reg, _type) \
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{ \
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.id = _id, \
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.name = _name, \
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.parent_data = _pdata, \
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.num_parents = ARRAY_SIZE(_pdata), \
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.flags = _flags, \
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.reg = _reg, \
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.type = _type, \
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}
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struct lgm_clk_ddiv_data {
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unsigned int id;
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const char *name;
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const struct clk_parent_data *parent_data;
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u8 flags;
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unsigned long div_flags;
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unsigned int reg;
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u8 shift0;
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u8 width0;
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u8 shift1;
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u8 width1;
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u8 shift_gate;
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u8 width_gate;
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u8 ex_shift;
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u8 ex_width;
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};
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#define LGM_DDIV(_id, _name, _pname, _flags, _reg, \
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_shft0, _wdth0, _shft1, _wdth1, \
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_shft_gate, _wdth_gate, _xshft, _df) \
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{ \
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.id = _id, \
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.name = _name, \
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.parent_data = &(const struct clk_parent_data){ \
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.fw_name = _pname, \
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.name = _pname, \
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}, \
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.flags = _flags, \
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.reg = _reg, \
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.shift0 = _shft0, \
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.width0 = _wdth0, \
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.shift1 = _shft1, \
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.width1 = _wdth1, \
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.shift_gate = _shft_gate, \
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.width_gate = _wdth_gate, \
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.ex_shift = _xshft, \
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.ex_width = 1, \
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.div_flags = _df, \
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}
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struct lgm_clk_branch {
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unsigned int id;
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enum lgm_clk_type type;
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const char *name;
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const struct clk_parent_data *parent_data;
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u8 num_parents;
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unsigned long flags;
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unsigned int mux_off;
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u8 mux_shift;
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u8 mux_width;
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unsigned long mux_flags;
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unsigned int mux_val;
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unsigned int div_off;
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u8 div_shift;
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u8 div_width;
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u8 div_shift_gate;
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u8 div_width_gate;
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unsigned long div_flags;
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unsigned int div_val;
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const struct clk_div_table *div_table;
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unsigned int gate_off;
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u8 gate_shift;
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unsigned long gate_flags;
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unsigned int gate_val;
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unsigned int mult;
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unsigned int div;
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};
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/* clock flags definition */
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#define CLOCK_FLAG_VAL_INIT BIT(16)
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#define MUX_CLK_SW BIT(17)
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#define GATE_CLK_HW BIT(18)
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#define DIV_CLK_NO_MASK BIT(19)
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#define LGM_MUX(_id, _name, _pdata, _f, _reg, \
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_shift, _width, _cf, _v) \
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{ \
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.id = _id, \
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.type = CLK_TYPE_MUX, \
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.name = _name, \
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.parent_data = _pdata, \
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.num_parents = ARRAY_SIZE(_pdata), \
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.flags = _f, \
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.mux_off = _reg, \
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.mux_shift = _shift, \
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.mux_width = _width, \
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.mux_flags = _cf, \
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.mux_val = _v, \
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}
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#define LGM_DIV(_id, _name, _pname, _f, _reg, _shift, _width, \
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_shift_gate, _width_gate, _cf, _v, _dtable) \
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{ \
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.id = _id, \
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.type = CLK_TYPE_DIVIDER, \
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.name = _name, \
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.parent_data = &(const struct clk_parent_data){ \
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.fw_name = _pname, \
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.name = _pname, \
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}, \
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.num_parents = 1, \
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.flags = _f, \
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.div_off = _reg, \
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.div_shift = _shift, \
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.div_width = _width, \
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.div_shift_gate = _shift_gate, \
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.div_width_gate = _width_gate, \
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.div_flags = _cf, \
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.div_val = _v, \
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.div_table = _dtable, \
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}
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#define LGM_GATE(_id, _name, _pname, _f, _reg, \
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_shift, _cf, _v) \
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{ \
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.id = _id, \
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.type = CLK_TYPE_GATE, \
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.name = _name, \
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.parent_data = &(const struct clk_parent_data){ \
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.fw_name = _pname, \
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.name = _pname, \
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}, \
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.num_parents = !_pname ? 0 : 1, \
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.flags = _f, \
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.gate_off = _reg, \
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.gate_shift = _shift, \
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.gate_flags = _cf, \
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.gate_val = _v, \
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}
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#define LGM_FIXED(_id, _name, _pname, _f, _reg, \
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_shift, _width, _cf, _freq, _v) \
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{ \
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.id = _id, \
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.type = CLK_TYPE_FIXED, \
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.name = _name, \
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.parent_data = &(const struct clk_parent_data){ \
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.fw_name = _pname, \
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.name = _pname, \
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}, \
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.num_parents = !_pname ? 0 : 1, \
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.flags = _f, \
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.div_off = _reg, \
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.div_shift = _shift, \
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.div_width = _width, \
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.div_flags = _cf, \
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.div_val = _v, \
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.mux_flags = _freq, \
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}
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#define LGM_FIXED_FACTOR(_id, _name, _pname, _f, _reg, \
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_shift, _width, _cf, _v, _m, _d) \
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{ \
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.id = _id, \
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.type = CLK_TYPE_FIXED_FACTOR, \
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.name = _name, \
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.parent_data = &(const struct clk_parent_data){ \
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.fw_name = _pname, \
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.name = _pname, \
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}, \
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.num_parents = 1, \
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.flags = _f, \
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.div_off = _reg, \
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.div_shift = _shift, \
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.div_width = _width, \
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.div_flags = _cf, \
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.div_val = _v, \
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.mult = _m, \
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.div = _d, \
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}
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static inline void lgm_set_clk_val(struct regmap *membase, u32 reg,
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u8 shift, u8 width, u32 set_val)
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{
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u32 mask = (GENMASK(width - 1, 0) << shift);
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regmap_update_bits(membase, reg, mask, set_val << shift);
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}
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static inline u32 lgm_get_clk_val(struct regmap *membase, u32 reg,
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u8 shift, u8 width)
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{
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u32 mask = (GENMASK(width - 1, 0) << shift);
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u32 val;
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if (regmap_read(membase, reg, &val)) {
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WARN_ONCE(1, "Failed to read clk reg: 0x%x\n", reg);
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return 0;
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}
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val = (val & mask) >> shift;
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return val;
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}
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int lgm_clk_register_branches(struct lgm_clk_provider *ctx,
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const struct lgm_clk_branch *list,
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unsigned int nr_clk);
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int lgm_clk_register_plls(struct lgm_clk_provider *ctx,
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const struct lgm_pll_clk_data *list,
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unsigned int nr_clk);
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int lgm_clk_register_ddiv(struct lgm_clk_provider *ctx,
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const struct lgm_clk_ddiv_data *list,
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unsigned int nr_clk);
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#endif /* __CLK_CGU_H */
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