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![Uwe Kleine-König](/assets/img/avatar_default.png)
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230312161512.2715500-30-u.kleine-koenig@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
120 lines
3 KiB
C
120 lines
3 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* clock framework for AMD FCH controller block
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*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/pci.h>
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#include <linux/platform_data/clk-fch.h>
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#include <linux/platform_device.h>
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/* Clock Driving Strength 2 register */
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#define CLKDRVSTR2 0x28
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/* Clock Control 1 register */
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#define MISCCLKCNTL1 0x40
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/* Auxiliary clock1 enable bit */
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#define OSCCLKENB 2
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/* 25Mhz auxiliary output clock freq bit */
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#define OSCOUT1CLK25MHZ 16
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#define ST_CLK_48M 0
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#define ST_CLK_25M 1
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#define ST_CLK_MUX 2
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#define ST_CLK_GATE 3
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#define ST_MAX_CLKS 4
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#define CLK_48M_FIXED 0
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#define CLK_GATE_FIXED 1
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#define CLK_MAX_FIXED 2
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/* List of supported CPU ids for clk mux with 25Mhz clk support */
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#define AMD_CPU_ID_ST 0x1576
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static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" };
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static struct clk_hw *hws[ST_MAX_CLKS];
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static const struct pci_device_id fch_pci_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_ST) },
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{ }
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};
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static int fch_clk_probe(struct platform_device *pdev)
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{
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struct fch_clk_data *fch_data;
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struct pci_dev *rdev;
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fch_data = dev_get_platdata(&pdev->dev);
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if (!fch_data || !fch_data->base)
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return -EINVAL;
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rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
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if (!rdev) {
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dev_err(&pdev->dev, "FCH device not found\n");
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return -ENODEV;
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}
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if (pci_match_id(fch_pci_ids, rdev)) {
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hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz",
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NULL, 0, 48000000);
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hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz",
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NULL, 0, 25000000);
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hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux",
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clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents),
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0, fch_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0,
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NULL);
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clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_48M]->clk);
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hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1",
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"oscout1_mux", 0, fch_data->base + MISCCLKCNTL1,
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OSCCLKENB, CLK_GATE_SET_TO_DISABLE, NULL);
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devm_clk_hw_register_clkdev(&pdev->dev, hws[ST_CLK_GATE],
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fch_data->name, NULL);
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} else {
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hws[CLK_48M_FIXED] = clk_hw_register_fixed_rate(NULL, "clk48MHz",
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NULL, 0, 48000000);
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hws[CLK_GATE_FIXED] = clk_hw_register_gate(NULL, "oscout1",
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"clk48MHz", 0, fch_data->base + MISCCLKCNTL1,
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OSCCLKENB, 0, NULL);
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devm_clk_hw_register_clkdev(&pdev->dev, hws[CLK_GATE_FIXED],
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fch_data->name, NULL);
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}
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pci_dev_put(rdev);
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return 0;
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}
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static void fch_clk_remove(struct platform_device *pdev)
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{
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int i, clks;
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struct pci_dev *rdev;
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rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
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if (!rdev)
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return;
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clks = pci_match_id(fch_pci_ids, rdev) ? CLK_MAX_FIXED : ST_MAX_CLKS;
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for (i = 0; i < clks; i++)
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clk_hw_unregister(hws[i]);
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pci_dev_put(rdev);
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}
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static struct platform_driver fch_clk_driver = {
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.driver = {
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.name = "clk-fch",
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.suppress_bind_attrs = true,
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},
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.probe = fch_clk_probe,
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.remove_new = fch_clk_remove,
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};
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builtin_platform_driver(fch_clk_driver);
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