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![]() A fairly standard release for SPI with the exception of a change to the API for specifying chip selects done in preparation for supporting devices with more than one chip select, this required some mechanical changes throughout the tree which have been cooking in -next happily for a while. There's also a new API to allow us to TPM chips on half duplex controllers. There's three commits in here that were mangled by a bad interaction between the alsa-devel mailing list software and b4, I didn't notice until there were merges on top with it being SPI not ALSA. It seemed clear enough to not be worth going back and fixing. - Refactoring in preparation for supporting multiple chip selects for a single device, needed by some flash devices, which required a change in the SPI device API visible throughout the tree. - Support for hardware assisted interaction with SPI TPMs on half duplex controllers, implemented on nVidia Tedra210 QuadSPI. - Optimisation for large transfers on fsl-cpm devices. - Cleanups around device property use which fix some sisues with fwnode. - Use of both void remove() and devm_platform_.*ioremap_resource(). - Support for AMD Pensando Elba, Amlogic A1, Cadence device mode, Intel MetorLake-S and StarFive J7110 QuadSPI. The final commit converting to DEV_PM_OPS() was applied late to fix a warning that was introduced by some of the earlier work. -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAmRIFQgACgkQJNaLcl1U h9BJOwf+JF2RySdn5g1LsyTndPZhLfw4iJgTHaMlnv5tiPHvYVYMM/mNMbMr5Znh Y2T0OUkzuRfOK273C+hItC1bTYFTa2cEbDb5dpmKBOZdQ3hjGsZQBvuH2bScUQ+a H7UgD3FYOJST6k6rRgZQxVMPePFrXAOaO1gmFWTR3v1EcEr2JeQnjZsmymFXcTnc CtPg9N3RvhVnq5aXuxSgQeyyKIjo4LJh/eZ2mexPIu0DeUq3MftaWwSwCXFIoeNC DMLA4mZWTgf/yt6JUALwLr+bIiJjb4qGjp3xGZ2wmX7zn73f9QQvuunKb1V4zbNF EdXLo2VjA9cZjsihenBaKeHnkfgNfA== =IRqY -----END PGP SIGNATURE----- Merge tag 'spi-v6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi updates from Mark Brown: "A fairly standard release for SPI with the exception of a change to the API for specifying chip selects done in preparation for supporting devices with more than one chip select, this required some mechanical changes throughout the tree which have been cooking in -next happily for a while. There's also a new API to allow us to support TPM chips on half duplex controllers. Summary: - Refactoring in preparation for supporting multiple chip selects for a single device, needed by some flash devices, which required a change in the SPI device API visible throughout the tree - Support for hardware assisted interaction with SPI TPMs on half duplex controllers, implemented on nVidia Tedra210 QuadSPI - Optimisation for large transfers on fsl-cpm devices - Cleanups around device property use which fix some sisues with fwnode - Use of both void remove() and devm_platform_.*ioremap_resource() - Support for AMD Pensando Elba, Amlogic A1, Cadence device mode, Intel MetorLake-S and StarFive J7110 QuadSPI" * tag 'spi-v6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (185 commits) spi: bcm63xx: use macro DEFINE_SIMPLE_DEV_PM_OPS spi: tegra210-quad: Enable TPM wait polling spi: Add TPM HW flow flag spi: bcm63xx: remove PM_SLEEP based conditional compilation spi: cadence-quadspi: use macro DEFINE_SIMPLE_DEV_PM_OPS spi: spi-cadence: Add support for Slave mode spi: spi-cadence: Switch to spi_controller structure spi: cadence-quadspi: fix suspend-resume implementations spi: dw: Add support for AMD Pensando Elba SoC spi: dw: Add AMD Pensando Elba SoC SPI Controller spi: cadence-quadspi: Disable the SPI before reconfiguring spi: cadence-quadspi: Update the read timeout based on the length spi: spi-loopback-test: Add module param for iteration length spi: add support for Amlogic A1 SPI Flash Controller dt-bindings: spi: add Amlogic A1 SPI controller spi: fsl-spi: No need to check transfer length versus word size spi: fsl-spi: Change mspi_apply_cpu_mode_quirks() to void spi: fsl-cpm: Use 16 bit mode for large transfers with even size spi: fsl-spi: Re-organise transfer bits_per_word adaptation spi: fsl-spi: Fix CPM/QE mode Litte Endian ... |
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