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bac139a846
This patch corrects the SPDX License Identifier style in header files related to drivers for USB Network devices. This patch gives an explicit block comment to the SPDX License Identifier. Changes made by using a script provided by Joe Perches here: https://lkml.org/lkml/2019/2/7/46. Suggested-by: Joe Perches <joe@perches.com> Signed-off-by: Nishad Kamdar <nishadkamdar@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
232 lines
6.5 KiB
C
232 lines
6.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* Aquantia Corp. Aquantia AQtion USB to 5GbE Controller
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* Copyright (C) 2003-2005 David Hollis <dhollis@davehollis.com>
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* Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
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* Copyright (C) 2002-2003 TiVo Inc.
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* Copyright (C) 2017-2018 ASIX
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* Copyright (C) 2018 Aquantia Corp.
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*/
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#ifndef __LINUX_USBNET_AQC111_H
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#define __LINUX_USBNET_AQC111_H
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#define URB_SIZE (1024 * 62)
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#define AQ_MCAST_FILTER_SIZE 8
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#define AQ_MAX_MCAST 64
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#define AQ_ACCESS_MAC 0x01
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#define AQ_FLASH_PARAMETERS 0x20
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#define AQ_PHY_POWER 0x31
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#define AQ_WOL_CFG 0x60
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#define AQ_PHY_OPS 0x61
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#define AQ_USB_PHY_SET_TIMEOUT 10000
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#define AQ_USB_SET_TIMEOUT 4000
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/* Feature. ********************************************/
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#define AQ_SUPPORT_FEATURE (NETIF_F_SG | NETIF_F_IP_CSUM |\
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NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |\
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NETIF_F_TSO | NETIF_F_HW_VLAN_CTAG_TX |\
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NETIF_F_HW_VLAN_CTAG_RX)
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#define AQ_SUPPORT_HW_FEATURE (NETIF_F_SG | NETIF_F_IP_CSUM |\
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NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |\
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NETIF_F_TSO | NETIF_F_HW_VLAN_CTAG_FILTER)
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#define AQ_SUPPORT_VLAN_FEATURE (NETIF_F_SG | NETIF_F_IP_CSUM |\
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NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |\
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NETIF_F_TSO)
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/* SFR Reg. ********************************************/
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#define SFR_GENERAL_STATUS 0x03
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#define SFR_CHIP_STATUS 0x05
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#define SFR_RX_CTL 0x0B
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#define SFR_RX_CTL_TXPADCRC 0x0400
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#define SFR_RX_CTL_IPE 0x0200
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#define SFR_RX_CTL_DROPCRCERR 0x0100
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#define SFR_RX_CTL_START 0x0080
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#define SFR_RX_CTL_RF_WAK 0x0040
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#define SFR_RX_CTL_AP 0x0020
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#define SFR_RX_CTL_AM 0x0010
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#define SFR_RX_CTL_AB 0x0008
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#define SFR_RX_CTL_AMALL 0x0002
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#define SFR_RX_CTL_PRO 0x0001
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#define SFR_RX_CTL_STOP 0x0000
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#define SFR_INTER_PACKET_GAP_0 0x0D
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#define SFR_NODE_ID 0x10
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#define SFR_MULTI_FILTER_ARRY 0x16
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#define SFR_MEDIUM_STATUS_MODE 0x22
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#define SFR_MEDIUM_XGMIIMODE 0x0001
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#define SFR_MEDIUM_FULL_DUPLEX 0x0002
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#define SFR_MEDIUM_RXFLOW_CTRLEN 0x0010
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#define SFR_MEDIUM_TXFLOW_CTRLEN 0x0020
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#define SFR_MEDIUM_JUMBO_EN 0x0040
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#define SFR_MEDIUM_RECEIVE_EN 0x0100
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#define SFR_MONITOR_MODE 0x24
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#define SFR_MONITOR_MODE_EPHYRW 0x01
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#define SFR_MONITOR_MODE_RWLC 0x02
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#define SFR_MONITOR_MODE_RWMP 0x04
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#define SFR_MONITOR_MODE_RWWF 0x08
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#define SFR_MONITOR_MODE_RW_FLAG 0x10
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#define SFR_MONITOR_MODE_PMEPOL 0x20
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#define SFR_MONITOR_MODE_PMETYPE 0x40
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#define SFR_PHYPWR_RSTCTL 0x26
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#define SFR_PHYPWR_RSTCTL_BZ 0x0010
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#define SFR_PHYPWR_RSTCTL_IPRL 0x0020
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#define SFR_VLAN_ID_ADDRESS 0x2A
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#define SFR_VLAN_ID_CONTROL 0x2B
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#define SFR_VLAN_CONTROL_WE 0x0001
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#define SFR_VLAN_CONTROL_RD 0x0002
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#define SFR_VLAN_CONTROL_VSO 0x0010
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#define SFR_VLAN_CONTROL_VFE 0x0020
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#define SFR_VLAN_ID_DATA0 0x2C
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#define SFR_VLAN_ID_DATA1 0x2D
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#define SFR_RX_BULKIN_QCTRL 0x2E
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#define SFR_RX_BULKIN_QCTRL_TIME 0x01
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#define SFR_RX_BULKIN_QCTRL_IFG 0x02
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#define SFR_RX_BULKIN_QCTRL_SIZE 0x04
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#define SFR_RX_BULKIN_QTIMR_LOW 0x2F
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#define SFR_RX_BULKIN_QTIMR_HIGH 0x30
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#define SFR_RX_BULKIN_QSIZE 0x31
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#define SFR_RX_BULKIN_QIFG 0x32
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#define SFR_RXCOE_CTL 0x34
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#define SFR_RXCOE_IP 0x01
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#define SFR_RXCOE_TCP 0x02
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#define SFR_RXCOE_UDP 0x04
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#define SFR_RXCOE_ICMP 0x08
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#define SFR_RXCOE_IGMP 0x10
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#define SFR_RXCOE_TCPV6 0x20
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#define SFR_RXCOE_UDPV6 0x40
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#define SFR_RXCOE_ICMV6 0x80
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#define SFR_TXCOE_CTL 0x35
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#define SFR_TXCOE_IP 0x01
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#define SFR_TXCOE_TCP 0x02
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#define SFR_TXCOE_UDP 0x04
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#define SFR_TXCOE_ICMP 0x08
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#define SFR_TXCOE_IGMP 0x10
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#define SFR_TXCOE_TCPV6 0x20
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#define SFR_TXCOE_UDPV6 0x40
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#define SFR_TXCOE_ICMV6 0x80
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#define SFR_BM_INT_MASK 0x41
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#define SFR_BMRX_DMA_CONTROL 0x43
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#define SFR_BMRX_DMA_EN 0x80
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#define SFR_BMTX_DMA_CONTROL 0x46
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#define SFR_PAUSE_WATERLVL_LOW 0x54
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#define SFR_PAUSE_WATERLVL_HIGH 0x55
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#define SFR_ARC_CTRL 0x9E
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#define SFR_SWP_CTRL 0xB1
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#define SFR_TX_PAUSE_RESEND_T 0xB2
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#define SFR_ETH_MAC_PATH 0xB7
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#define SFR_RX_PATH_READY 0x01
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#define SFR_BULK_OUT_CTRL 0xB9
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#define SFR_BULK_OUT_FLUSH_EN 0x01
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#define SFR_BULK_OUT_EFF_EN 0x02
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#define AQ_FW_VER_MAJOR 0xDA
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#define AQ_FW_VER_MINOR 0xDB
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#define AQ_FW_VER_REV 0xDC
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/*PHY_OPS**********************************************************************/
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#define AQ_ADV_100M BIT(0)
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#define AQ_ADV_1G BIT(1)
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#define AQ_ADV_2G5 BIT(2)
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#define AQ_ADV_5G BIT(3)
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#define AQ_ADV_MASK 0x0F
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#define AQ_PAUSE BIT(16)
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#define AQ_ASYM_PAUSE BIT(17)
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#define AQ_LOW_POWER BIT(18)
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#define AQ_PHY_POWER_EN BIT(19)
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#define AQ_WOL BIT(20)
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#define AQ_DOWNSHIFT BIT(21)
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#define AQ_DSH_RETRIES_SHIFT 0x18
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#define AQ_DSH_RETRIES_MASK 0xF000000
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#define AQ_WOL_FLAG_MP 0x2
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/******************************************************************************/
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struct aqc111_wol_cfg {
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u8 hw_addr[6];
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u8 flags;
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u8 rsvd[283];
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} __packed;
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#define WOL_CFG_SIZE sizeof(struct aqc111_wol_cfg)
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struct aqc111_data {
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u16 rxctl;
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u8 rx_checksum;
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u8 link_speed;
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u8 link;
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u8 autoneg;
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u32 advertised_speed;
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struct {
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u8 major;
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u8 minor;
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u8 rev;
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} fw_ver;
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u32 phy_cfg;
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u8 wol_flags;
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};
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#define AQ_LS_MASK 0x8000
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#define AQ_SPEED_MASK 0x7F00
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#define AQ_SPEED_SHIFT 0x0008
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#define AQ_INT_SPEED_5G 0x000F
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#define AQ_INT_SPEED_2_5G 0x0010
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#define AQ_INT_SPEED_1G 0x0011
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#define AQ_INT_SPEED_100M 0x0013
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/* TX Descriptor */
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#define AQ_TX_DESC_LEN_MASK 0x1FFFFF
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#define AQ_TX_DESC_DROP_PADD BIT(28)
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#define AQ_TX_DESC_VLAN BIT(29)
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#define AQ_TX_DESC_MSS_MASK 0x7FFF
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#define AQ_TX_DESC_MSS_SHIFT 0x20
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#define AQ_TX_DESC_VLAN_MASK 0xFFFF
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#define AQ_TX_DESC_VLAN_SHIFT 0x30
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#define AQ_RX_HW_PAD 0x02
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/* RX Packet Descriptor */
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#define AQ_RX_PD_L4_ERR BIT(0)
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#define AQ_RX_PD_L3_ERR BIT(1)
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#define AQ_RX_PD_L4_TYPE_MASK 0x1C
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#define AQ_RX_PD_L4_UDP 0x04
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#define AQ_RX_PD_L4_TCP 0x10
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#define AQ_RX_PD_L3_TYPE_MASK 0x60
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#define AQ_RX_PD_L3_IP 0x20
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#define AQ_RX_PD_L3_IP6 0x40
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#define AQ_RX_PD_VLAN BIT(10)
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#define AQ_RX_PD_RX_OK BIT(11)
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#define AQ_RX_PD_DROP BIT(31)
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#define AQ_RX_PD_LEN_MASK 0x7FFF0000
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#define AQ_RX_PD_LEN_SHIFT 0x10
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#define AQ_RX_PD_VLAN_SHIFT 0x20
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/* RX Descriptor header */
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#define AQ_RX_DH_PKT_CNT_MASK 0x1FFF
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#define AQ_RX_DH_DESC_OFFSET_MASK 0xFFFFE000
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#define AQ_RX_DH_DESC_OFFSET_SHIFT 0x0D
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static struct {
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unsigned char ctrl;
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unsigned char timer_l;
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unsigned char timer_h;
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unsigned char size;
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unsigned char ifg;
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} AQC111_BULKIN_SIZE[] = {
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/* xHCI & EHCI & OHCI */
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{7, 0x00, 0x01, 0x1E, 0xFF},/* 10G, 5G, 2.5G, 1G */
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{7, 0xA0, 0x00, 0x14, 0x00},/* 100M */
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/* Jumbo packet */
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{7, 0x00, 0x01, 0x18, 0xFF},
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};
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#endif /* __LINUX_USBNET_AQC111_H */
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