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![Krzysztof Kozlowski](/assets/img/avatar_default.png)
The driver can match only via the DT table so the table should be always used and the of_match_ptr does not have any sense (this also allows ACPI matching via PRP0001, even though it might not be relevant here). This also fixes a !CONFIG_OF error with W=1: drivers/soc/renesas/pwc-rzv2m.c:124:34: error: ‘rzv2m_pwc_of_match’ defined but not used [-Werror=unused-const-variable=] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230312132650.352796-2-krzysztof.kozlowski@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
141 lines
3.4 KiB
C
141 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2023 Renesas Electronics Corporation
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*/
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#include <linux/delay.h>
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#include <linux/gpio/driver.h>
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#include <linux/platform_device.h>
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#include <linux/reboot.h>
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#define PWC_PWCRST 0x00
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#define PWC_PWCCKEN 0x04
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#define PWC_PWCCTL 0x50
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#define PWC_GPIO 0x80
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#define PWC_PWCRST_RSTSOFTAX 0x1
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#define PWC_PWCCKEN_ENGCKMAIN 0x1
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#define PWC_PWCCTL_PWOFF 0x1
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struct rzv2m_pwc_priv {
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void __iomem *base;
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struct device *dev;
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struct gpio_chip gp;
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DECLARE_BITMAP(ch_en_bits, 2);
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};
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static void rzv2m_pwc_gpio_set(struct gpio_chip *chip, unsigned int offset,
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int value)
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{
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struct rzv2m_pwc_priv *priv = gpiochip_get_data(chip);
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u32 reg;
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/* BIT 16 enables write to BIT 0, and BIT 17 enables write to BIT 1 */
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reg = BIT(offset + 16);
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if (value)
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reg |= BIT(offset);
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writel(reg, priv->base + PWC_GPIO);
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assign_bit(offset, priv->ch_en_bits, value);
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}
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static int rzv2m_pwc_gpio_get(struct gpio_chip *chip, unsigned int offset)
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{
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struct rzv2m_pwc_priv *priv = gpiochip_get_data(chip);
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return test_bit(offset, priv->ch_en_bits);
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}
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static int rzv2m_pwc_gpio_direction_output(struct gpio_chip *gc,
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unsigned int nr, int value)
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{
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if (nr > 1)
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return -EINVAL;
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rzv2m_pwc_gpio_set(gc, nr, value);
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return 0;
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}
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static const struct gpio_chip rzv2m_pwc_gc = {
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.label = "gpio_rzv2m_pwc",
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.owner = THIS_MODULE,
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.get = rzv2m_pwc_gpio_get,
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.set = rzv2m_pwc_gpio_set,
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.direction_output = rzv2m_pwc_gpio_direction_output,
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.can_sleep = false,
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.ngpio = 2,
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.base = -1,
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};
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static int rzv2m_pwc_poweroff(struct sys_off_data *data)
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{
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struct rzv2m_pwc_priv *priv = data->cb_data;
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writel(PWC_PWCRST_RSTSOFTAX, priv->base + PWC_PWCRST);
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writel(PWC_PWCCKEN_ENGCKMAIN, priv->base + PWC_PWCCKEN);
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writel(PWC_PWCCTL_PWOFF, priv->base + PWC_PWCCTL);
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mdelay(150);
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dev_err(priv->dev, "Failed to power off the system");
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return NOTIFY_DONE;
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}
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static int rzv2m_pwc_probe(struct platform_device *pdev)
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{
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struct rzv2m_pwc_priv *priv;
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int ret;
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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/*
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* The register used by this driver cannot be read, therefore set the
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* outputs to their default values and initialize priv->ch_en_bits
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* accordingly. BIT 16 enables write to BIT 0, BIT 17 enables write to
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* BIT 1, and the default value of both BIT 0 and BIT 1 is 0.
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*/
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writel(BIT(17) | BIT(16), priv->base + PWC_GPIO);
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bitmap_zero(priv->ch_en_bits, 2);
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priv->gp = rzv2m_pwc_gc;
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priv->gp.parent = pdev->dev.parent;
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priv->gp.fwnode = dev_fwnode(&pdev->dev);
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ret = devm_gpiochip_add_data(&pdev->dev, &priv->gp, priv);
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if (ret)
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return ret;
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if (device_property_read_bool(&pdev->dev, "renesas,rzv2m-pwc-power"))
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ret = devm_register_power_off_handler(&pdev->dev,
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rzv2m_pwc_poweroff, priv);
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return ret;
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}
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static const struct of_device_id rzv2m_pwc_of_match[] = {
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{ .compatible = "renesas,rzv2m-pwc" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, rzv2m_pwc_of_match);
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static struct platform_driver rzv2m_pwc_driver = {
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.probe = rzv2m_pwc_probe,
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.driver = {
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.name = "rzv2m_pwc",
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.of_match_table = rzv2m_pwc_of_match,
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},
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};
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module_platform_driver(rzv2m_pwc_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Fabrizio Castro <castro.fabrizio.jz@renesas.com>");
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MODULE_DESCRIPTION("Renesas RZ/V2M PWC driver");
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